BAD COLUMN HANDLING IN FLASH MEMORY

• US 20180024880A1
• Filed: 09/20/2017
• Published: 01/25/2018
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Yurzola, Damian, Sharon, Eran, Alrod, Idan, Altshuler, Michael, Kotagiri, Madhuri, Nagabhirava, Rajeev
• Granted Patent: US 10,459,787 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

Claims

1. A nonvolatile memory system comprising:

a memory array having a plurality of columns, each of the plurality of columns comprising one or more bit lines; and

a soft-input error correction code decoder configured to receive hard data and soft data for at least one bad column of the plurality of columns and further configured to decode the hard data in combination with the soft data to generate decoded data,

wherein the soft data comprises compressed information including indication of locations of bad data within the at least one bad column, and

wherein the locations of bad data are replaced by indications of low likelihood.

2. The nonvolatile memory system of claim 1, wherein the at least one bad column comprises at least one defective bit line.

3. The nonvolatile memory system of claim 1, wherein the compressed information comprises compressed bit line location information.

4. The nonvolatile memory system of claim 1, wherein the compressed information is obtained by dividing the plurality of columns into a plurality of sections and aggregating the plurality of sections into a folded page.

5. The nonvolatile memory system of claim 4, wherein a folded page column within the folded page is indicated as a bad column based upon a location of the folded page column corresponding to a bad column location in any of the plurality of sections.

6. The nonvolatile memory system of claim 1, wherein the memory array is a NAND flash memory array.

7. The nonvolatile memory system of claim 1, wherein the plurality of columns comprise a plurality of non-redundant columns having the at least one bad column, and one or more redundant columns.

8. The nonvolatile memory system of claim 7, wherein a portion of the at least one bad columns is replaced by the one or more redundant columns.

9. The nonvolatile memory system of claim 7, wherein at least one of the one or more redundant columns is configured to store error correction code data.

10. The nonvolatile memory system of claim 7, wherein each of the at least one bad column is assigned a rank between a high rank and a low rank.

11. A memory array comprising:

a plurality of bad columns, each of the plurality of bad columns comprising a plurality of bit lines, wherein each of the plurality of bad columns is assigned a high rank or a low rank according to a number of bad bit lines in that column;

one or more redundant columns that replace one or more of the plurality of bad columns based upon the ranking;

a record that records the plurality of bad columns having the low rank, the plurality of bad columns having the low rank storing data; and

a soft-input error correction code decoder in communication with the record, the soft-input error correction code decoder configured to identify the data from the plurality of bad columns having the low rank from the record and apply a low likelihood to the data.

12. The memory array of claim 11, wherein the one or more redundant columns are further configured to store error correction code data.

13. The memory array of claim 11, wherein a number of bad bit lines in the plurality of bad columns with the high rank is greater than a predetermined number and the number of bad bit lines in the plurality of bad columns with the low rank is less than or equal to the predetermined number.

14. The memory array of claim 11, wherein the plurality of bad columns with the low rank are ranked according to error correction code results from the data stored in the plurality of bad columns.

15. The memory array of claim 11, wherein the memory array is a NAND flash memory array.

16. A memory array comprising:

a plurality of columns having a plurality of non-redundant columns and one or more redundant columns, wherein the plurality of non-redundant columns comprise a plurality of bad columns,

wherein, based upon a number of the plurality of bad columns being equal to or less than a threshold, each of the plurality of bad columns is replaced by the one or more redundant columns, and

wherein, based upon the number of the plurality of bad columns being greater than the threshold, a first portion of the plurality of plurality of bad columns is replaced by the one or more redundant columns and a second portion of the plurality of bad columns is decoded by a soft input error correction code decoder based upon a combination of soft data and hard data.

17. The memory array of claim 16, wherein based upon the number of the plurality of bad columns being greater than the threshold, each of the plurality of bad columns is ranked between a high rank and a low rank based upon a criteria, and wherein the plurality of bad columns in the first portion comprise high ranked bad columns and the plurality of bad columns in the second portion comprise low ranked bad columns.

18. The memory array of claim 17, wherein the criteria is bad bit lines, and wherein the plurality of bad columns in which a number of the bad bit lines exceed a predetermined number are assigned the high rank, and wherein the plurality of bad columns in which the number of the bad bit lines is less than or equal to the predetermined number are assigned the low rank.

19. The memory array of claim 16, wherein the second portion of the plurality of bad columns is compressed into a folded page that indicates locations of each of the plurality of bad columns to obtain the soft data.

20. The memory array of claim 19, wherein the locations of each of the plurality of bad columns are replaced by a low likelihood indication.