BAD COLUMN MANAGEMENT WITH DATA SHUFFLE IN PIPELINE

• US 20180024948A1
• Filed: 03/14/2017
• Published: 01/25/2018
• Est. Priority Date: 07/20/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Tsai, Wanfang, Li, Yan
• Granted Patent: US 10,120,816 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 29/84 with improved access time or stability
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

Claims

1. An apparatus, comprising:

an input register configured to store a first set of data from one or more memory arrays;

a temporary buffer;

a control circuit configured to write a subset of the first set of data to the temporary buffer, the input register configured to store a second set of data from the one or more memory arrays;

an output register; and

a control circuit configured to detect that the second set of data does not include data associated with a bad column within the one or more memory arrays and configured to write the subset of the first set of data from the temporary buffer to the output register in response to the detection that the second set of data does not include data associated with a bad column, the control circuit configured to write a first subset of the second set of data from the input register to the output register and configured to write a second subset of the second set of data from the input register to the temporary buffer.

2. The apparatus of claim 1, wherein:

the input register comprises data storage for M bytes of data;

the output register comprises data storage for M bytes of data; and

the control circuit configured to write N bytes of the first set of data less than the M bytes of data from the temporary buffer to the output register and configured to write M−

N bytes of the second set of data from the input register to the output register.

3. The apparatus of claim 2, wherein:

the control circuit configured to write N bytes of the second set of data from the input register to the temporary buffer.

4. The apparatus of claim 1, wherein:

the input register configured to store a third set of data from the one or more memory arrays subsequent to storing the second set of data; and

the control circuit configured to detect that the third set of data includes data associated with a bad column within the one or more memory arrays and configured to write the second subset of a second set of data from the temporary buffer to the output register, the control circuit configured to write a first subset of the third set of data from the input register to the output register and configured to write a second subset of the third set of data from the input register to the temporary buffer.

5. The apparatus of claim 4, wherein:

the input register comprises data storage for M bytes of data;

the output register comprises data storage for M bytes of data; and

the control circuit configured to write N bytes of the second set of data less than the M bytes of data from the temporary buffer to the output register and configured to write M−

N bytes of the third set of data from the input register to the output register.

6. The apparatus of claim 5, wherein:

the control circuit configured to detect that the third set of data includes X bytes of data associated with one or more bad columns within the one or more memory arrays and configured to write N−

X bytes of the third set of data from the input register to the temporary buffer.

7. The apparatus of claim 1, wherein:

the input register configured to store the second set of data from one or more memory arrays at a second point in time and configured to store a third set of data from the one or more memory arrays at a third point in time subsequent to the second point in time;

the input register configured to store M bytes of data;

the temporary buffer configured to store N bytes of data less than the M bytes of data; and

the control circuit configured to detect that the third set of data maps to bad column data of X bytes and that M−

X bytes is less than M−

N bytes, the control circuit configured to stall the transfer of data from the output register and write M−

X bytes of the third set of data from the input register to the temporary buffer.

8. The apparatus of claim 1, wherein:

the one or more memory arrays comprise one of three-dimensional memory arrays or vertical NAND memory arrays.

9. The apparatus of claim 1, wherein:

the output register transfers data to a bi-directional buffer.

10. The apparatus of claim 10, wherein:

the one or more memory arrays comprise a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

11. A system, comprising:

an input register configured to store a first set of data from one or more memory arrays and subsequently store a second set of data from the one or more memory arrays;

an output register;

a bad column detection circuit configured to detect that the second set of data does not include data associated with one or more bad columns within the one or more memory arrays;

a data transfer circuit configured to transfer a subset of a first set of data from a temporary buffer to the output register; and

means for transferring a first subset of the second set of data from the input register to the output register and writing a second subset of the second set of data from the input register to the temporary buffer.

12. The system of claim 11, further comprising:

means for writing N bytes of the first set of data less than M bytes of data from the temporary buffer to the output register and writing M−

N bytes of the second set of data from the input register to the output register, the input register comprises data storage for the M bytes of data and the output register comprises data storage for the M bytes of data.

13. The system of claim 12, further comprising:

means for writing N bytes of the second set of data from the input register to the temporary buffer.

14. The system of claim 11, wherein:

the one or more memory arrays comprise one of three-dimensional memory arrays or vertical NAND memory arrays.

15. An apparatus, comprising:

an input register configured to store a second set of data to be written to one or more memory arrays;

a temporary buffer;

an output register; and

a control circuit configured to detect that the output register does not have a data mapping to a bad column within the one or more memory arrays and configured to write a subset of a first set of data from the temporary buffer to the output register in response to detection that the output register does not have a data mapping to a bad column within the one or more memory arrays, the control circuit configured to write a first subset of the second set of data from the input register to the output register and configured to write a second subset of the second set of data from the input register to the temporary buffer.

16. The apparatus of claim 15, wherein:

the input register comprises data storage for M bytes of data;

the output register comprises data storage for M bytes of data; and

the control circuit configured to write N bytes of the first set of data less than the M bytes of data from the temporary buffer to the output register and configured to write M−

N bytes of the second set of data from the input register to the output register.

17. The apparatus of claim 16, wherein:

the control circuit configured to write N bytes of the second set of data from the input register to the temporary buffer.

18. The apparatus of claim 15, wherein:

the input register configured to store a third set of data to be written to the one or more memory arrays; and

the control circuit configured to detect that the output register does have a data mapping to a bad column within the one or more memory arrays and configured to write the second subset of the second set of data from the temporary buffer to the output register in response to detection that the output register does have a data mapping to a bad column within the one or more memory arrays, the control circuit configured to write a first subset of the third set of data from the input register to the output register and configured to write a second subset of the third set of data from the input register to the temporary buffer.

19. The apparatus of claim 18, wherein:

the input register comprises data storage for M bytes of data;

the output register comprises data storage for M bytes of data; and

the control circuit configured to detect that the output register maps to bad column data of X bytes, the control circuit configured to write N bytes of the second set of data less than the M bytes of data from the temporary buffer to the output register and configured to write M−

N−

X bytes of the third set of data from the input register to the output register, the control circuit configured to write N+X bytes of the third set of data from the input register to the temporary buffer.

20. The apparatus of claim 15, wherein:

the one or more memory arrays comprise one of three-dimensional memory arrays or vertical NAND memory arrays.