STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP INTERFACE

• US 20180024963A1
• Filed: 07/21/2016
• Published: 01/25/2018
• Est. Priority Date: 07/21/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DREPS, DANIEL M., JAYARAMAN, PRASANNA, SPEAR, MICHAEL B.
• Granted Patent: US 10,901,936 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A method, system, and/or computer program product controls transitions from a first bandwidth to a second bandwidth in a bus within a multi-processor computer. A bus controller predicts a bandwidth transition requirement for a bus in a multi-processor computer, and transitions the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement. The bus controller checks an actual transitioning requirement of the bus in the computer, such that the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processor processors in the computer. In response to the actual transitioning requirement matching the predicted bandwidth transition requirement, the bus controller directions a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

Claims

1. A method comprising:

predicting, by a bus controller, a bandwidth transition requirement for a bus in a multi-processor computer;

transitioning, by the bus controller, the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement;

checking, by the bus controller, an actual transitioning requirement of the bus in the computer, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer; and

in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, directing, by the bus controller, a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

2. The method of claim 1, wherein the first bandwidth is higher than the second bandwidth.

3. The method of claim 1, wherein the first bandwidth is lower than the second bandwidth.

4. The method of claim 1, wherein the transition from first bandwidth to second bandwidth occurs in multiple phases, and wherein the method further comprises:

validating, by the bus controller, the continuation of the transition of the bus from the first bandwidth to the second bandwidth at a completion of each of the multiple phases.

5. The method of claim 1, wherein the transition from first bandwidth to second bandwidth occurs in multiple phases, and wherein the method further comprises:

validating, by the bus controller, the transition of the bus from the first bandwidth to the second bandwidth during each of the multiple phases.

6. The method of claim 1, wherein the predefined stage of the one or more processors occurs when one or more of the processors implement a new type of workload.

7. The method of claim 1, wherein the predefined stage of the one or more processors occurs when one or more of the processors retrieves a new set of data during a pending workload in the one or more processors.

8. The method of claim 1, further comprising:

in response to the actual transitioning requirement not matching the predicted bandwidth transition requirement, aborting the transitioning of the bus from the first bandwidth to the second bandwidth.

9. The method of claim 1, wherein the bus comprises a data line and a clock line, and wherein the method further comprises:

transitioning, by the bus controller, the data line from the first bandwidth to the second bandwidth; and

in response to the data line transitioning from the first bandwidth to the second bandwidth, adjusting, by the bus controller, the clock line to match needs of the transitioned data line.

10. The method of claim 1, wherein the multi-processor computer comprises a separate bus between each pair of processors within the multi-processor computer, wherein each processor in the multi-processor computer comprises a separate bus controller, wherein each processor in the multi-processor computer comprises a processor core, and wherein the method further comprises:

negotiating a staged sequence of transitioning from the first bandwidth to the second bandwidth for each bus connecting said each pair of processors; and

selectively aborting or completing the transitioning from the first bandwidth to the second bandwidth for each bus connecting said each pair of processors based on outputs from processor cores in the pair of processors, wherein the outputs are processed by bus controllers in the pair of processors to determine whether to abort or complete the transitioning from the first bandwidth to the second bandwidth for each bus connecting said each pair of processors based on predicted workloads in the cores.

11. A computer program product for transitioning a bus from a first bandwidth to a second bandwidth, the computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code readable and executable by a processor to perform a method comprising:

predicting a bandwidth transition requirement for a bus in a multi-processor computer;

transitioning the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement;

checking an actual transitioning requirement of the bus in the computer, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer; and

directing, in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

12. The computer program product of claim 11, wherein the first bandwidth is higher than the second bandwidth.

13. The computer program product of claim 11, wherein the first bandwidth is lower than the second bandwidth.

14. The computer program product of claim 11, wherein the bus controller predicts the bandwidth transition requirement of the bus based on a workload type for a pending workload in the one or more processors.

15. The computer program product of claim 14, wherein the method further comprises:

detecting an average cycles/data ratio for the pending workload, wherein the average cycles/data ratio describes an average number of clock cycles required to perform data transfers for the workload type of the pending workload; and

transitioning the bus from the first bandwidth to the second bandwidth based on the average cycles/data ratio for the workload type of the pending workload.

16. The computer program product of claim 11, wherein the predefined stage of the one or more processors occurs when one or more of the processors retrieves a new set of data during a pending workload in the one or more processors.

17. The computer program product of claim 11 wherein the method further comprises:

in response to the actual transitioning requirement not matching the predicted bandwidth transition requirement, aborting the transitioning of the bus from the first bandwidth to the second bandwidth.

18. The computer program product of claim 11, wherein the bus comprises a data line and a clock line, and wherein the method further comprises:

transitioning the data line from the first bandwidth to the second bandwidth; and

in response to the data line transitioning from the first bandwidth to the second bandwidth, adjusting the clock line to match needs of the transitioned data line.

19. A computer system comprising one or more processors, one or more computer readable memories, and one or more computer readable storage mediums, and program instructions stored on at least one of the one or more storage mediums for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:

program instructions to predict a bandwidth transition requirement for a bus in a multi-processor computer, wherein the bandwidth transition requirement of the bus is predicted based on a workload type for a pending workload in one or more processors in the multi-processor computer;

program instructions to detect an average cycles/data ratio for the pending workload, wherein the average cycles/data ratio describes an average number of clock cycles required to perform data transfers for the workload type of the pending workload; and

program instructions to transition the bus from a first bandwidth to a second bandwidth based on the average cycles/data ratio for the workload type of the pending workload;

program instructions to check an actual transitioning requirement of the bus in the processor, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer; and

program instructions to, in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, direct a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

20. The computer system of claim 19, wherein the bus comprises a data line and a clock line, and wherein the computer system further comprises:

program instructions to transition the data line from the first bandwidth to the second bandwidth; and

program instructions to, in response to the data line transitioning from the first bandwidth to the second bandwidth, adjust the clock line to match needs of the transitioned data line.