×

STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP INTERFACE

  • US 20180024963A1
  • Filed: 07/21/2016
  • Published: 01/25/2018
  • Est. Priority Date: 07/21/2016
  • Status: Active Grant
First Claim
Patent Images

1. A method comprising:

  • predicting, by a bus controller, a bandwidth transition requirement for a bus in a multi-processor computer;

    transitioning, by the bus controller, the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement;

    checking, by the bus controller, an actual transitioning requirement of the bus in the computer, wherein the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processors in the multi-processor computer; and

    in response to the actual transitioning requirement matching the predicted bandwidth transition requirement, directing, by the bus controller, a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×