INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY

• US 20180025970A1
• Filed: 07/25/2016
• Published: 01/25/2018
• Est. Priority Date: 07/25/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kao, Min-Feng, Yaung, Dun-Nian, Lin, Hsing-Chih, Liu, Jen-Cheng, Huang, Kuan-Chieh
• Granted Patent: US 10,510,592 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Claims

1. An integrated circuit (IC) comprising:

a semiconductor substrate;

a first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure respectively under and over the semiconductor substrate;

a first electronic device and a second electronic device between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure;

a through substrate via (TSV) extending through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure;

a pad structure over and electrically coupled to the second BEOL interconnect structure, wherein the pad structure is at a top surface of the IC; and

a dielectric layer over the semiconductor substrate, wherein the dielectric layer extends continuously from direct contact with the semiconductor substrate to direct contact with the pad structure.

2. The IC according to claim 1, wherein the first and second BEOL interconnect structures each comprise an interlayer dielectric (ILD) layer, via layers, and wiring layers, wherein the via and wiring layers are alternatingly stacked within the ILD layer, and wherein the second electronic device is defined by at least one of the wiring layers of the second BEOL interconnect structure.

7. The IC according to claim 1, further comprising:

an epitaxial layer in the second BEOL interconnect structure, wherein the second electronic device is in the epitaxial layer.

8. The IC according to claim 7, wherein the second BEOL interconnect structure comprises a pair of wiring layers and a via layer, wherein the via layer extends from a wiring layer of the pair to another wiring layer of the pair, and wherein the epitaxial layer is spaced between the wiring layers of the pair.

9. The IC according to claim 7, wherein the second electronic device comprises a pair of source/drain regions and a gate electrode, wherein the source/drain regions are in a top of the epitaxial layer, and wherein the gate electrode is laterally between the source/drain regions.

10. The IC according to claim 1, further comprising:

a support structure under the first BEOL interconnect structure; and

a bond interface layer between the support structure and the first BEOL interconnect structure, wherein the bond interface layer bonds the support structure to the first BEOL interconnect structure.

11. The IC according to claim 10, wherein the support structure comprises:

a second semiconductor substrate; and

a third BEOL interconnect structure over the second semiconductor substrate, wherein the bond interface layer bonds and electrically couples the third BEOL interconnect structure to the first BEOL interconnect structure.

21. The IC according to claim 1, further comprising:

a solder bump overlying and directly contacting the pad structure.

3. (canceled)

4. An integrated circuit (IC) comprising:

a semiconductor substrate;

a first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure respectively under and over the semiconductor substrate;

a first electronic device and a second electronic device between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure, wherein the first electronic device is in a bottom of the semiconductor substrate, between the semiconductor substrate and the first BEOL interconnect structure, and wherein the second electronic device is in a top of the semiconductor, between the semiconductor substrate and the second BEOL interconnect structure; and

a through substrate via (TSV) extending through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure.

5. The IC according to claim 4, wherein the second electronic device comprises a pair of source/drain regions and a gate electrode, wherein the source/drain regions are in the top of the semiconductor substrate, and wherein the gate electrode is laterally between the source/drain regions.

6. The IC according to claim 5, wherein the gate electrode is spaced over the semiconductor substrate by a gate dielectric layer that is arranged over and contacts a top surface of the TSV.

12. A method for manufacturing an integrated circuit (IC), the method comprising:

forming a first back-end-of-line (BEOL) interconnect structure and a first electronic device on a bottom of a semiconductor substrate, wherein the first electronic device is between the semiconductor substrate and a bottom of the first BEOL interconnect structure;

forming a through substrate via (TSV) extending through the semiconductor substrate to the first BEOL interconnect structure; and

after the forming of the first BEOL interconnect structure, forming a second BEOL interconnect structure and a second electronic device on a top of the semiconductor substrate, wherein the second BEOL interconnect structure contacts the TSV, wherein the second electronic device is between the semiconductor substrate and a top of the second BEOL interconnect structure, wherein the forming of the second BEOL interconnect structure comprises repeatedly depositing and patterning a conductive layer on the semiconductor substrate.

13. The method according to claim 12, further comprising:

before forming the TSV, bonding the semiconductor substrate to a bulk substrate of glass or a semiconductor material through the first BEOL interconnect structure.

14. The method according to claim 12, further comprising:

forming a third back-end-of-line (BEOL) interconnect structure and a third electronic device over a second semiconductor substrate, wherein the third electronic device is between the second semiconductor substrate and a top of the third BEOL interconnect structure; and

before forming the TSV, bonding the semiconductor substrate to the third BEOL interconnect structure through the first BEOL interconnect structure.

15. The method according to claim 12, wherein forming the second BEOL interconnect structure comprises forming via layers and wiring layers alternatingly stacked, and wherein forming the second electronic device comprises forming at least one of the wiring layers with a layout of the second electronic device.

16. The method according to claim 12, further comprising:

forming the first and second electronic devices as transistors respectively in the bottom of the semiconductor substrate and the top of the semiconductor substrate.

17. The method according to claim 12, wherein forming the second BEOL interconnect structure and the second electronic device comprise:

forming a wiring layer over the semiconductor substrate;

forming an epitaxial layer spaced over the wiring layer;

forming the second electronic device in the epitaxial layer; and

forming another wiring layer over the second electronic device.

18. The method according to claim 17, wherein forming the second BEOL interconnect structure and the second electronic device further comprises forming an interlayer dielectric (ILD) layer covering the wiring layer before forming the epitaxial layer, and wherein forming the epitaxial layer comprises:

implanting ions into a third semiconductor substrate to form an in-depth weakened layer spaced between top and bottom surfaces of the third semiconductor substrate;

bonding the third semiconductor substrate to the ILD layer; and

cleaving the third semiconductor substrate along the in-depth weakened layer to remove part of the third substrate from the ILD layer.

22. The method according to claim 12, wherein the second BEOL interconnect structure comprises a first wire and a second wire over the first wire, wherein the forming of the second BEOL interconnect structure comprises depositing a first conductive layer covering the semiconductor substrate and the first BEOL interconnect structure, patterning the first conductive layer to define the first wire, depositing a second conductive layer covering the semiconductor substrate and the first wire, and patterning the second conductive layer to define the second wire.

23. The method according to claim 12, wherein the first BEOL interconnect structure is formed directly on the bottom of the semiconductor substrate, and wherein the second BEOL interconnect structure is formed directly on the top of the semiconductor substrate.

19. (canceled)

20. (canceled)