SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20180026045A1
• Filed: 09/13/2016
• Published: 01/25/2018
• Est. Priority Date: 07/22/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: HU, Ming
• Granted Patent: US 10,461,090 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor memory device according to an embodiment comprises a substrate, a plurality of first conductive films, a memory columnar body, and a first structure. The plurality of first conductive films are stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction. The memory columnar body extends in the first direction and has a side surface covered by the plurality of first conductive films. The first structure extends in the second direction and divides the plurality of first conductive films in the third direction. Moreover, each of the memory columnar body and the first structure comprises: a memory insulating film provided on a side surface of the first conductive film; and a first semiconductor layer provided on a side surface of the memory insulating film.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a plurality of first conductive films stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction;

a memory columnar body extending in the first direction and having a side surface covered by the plurality of first conductive films; and

a first structure extending in the second direction and dividing the plurality of first conductive films in the third direction,

each of the memory columnar body and the first structure comprising;

a memory insulating film provided on a side surface of the first conductive film; and

a first semiconductor layer provided on a side surface of the memory insulating film.

2. The semiconductor memory device according to claim 1, wherein

the memory insulating film comprises a first insulating film, a charge accumulation film, and a second insulating film provided sequentially on the side surface of the first conductive film.

3. The semiconductor memory device according to claim 1, comprising:

a memory plane provided above the substrate and including the plurality of first conductive films and the memory columnar body; and

a plurality of the first structures arranged at first intervals in the third direction,

wherein the memory plane is divided into a plurality of sub-planes by the plurality of first structures.

4. The semiconductor memory device according to claim 3, further comprising

a plurality of second structures arranged in the third direction at second intervals smaller than the first intervals, extending in the second direction, and dividing the plurality of first conductive films in the third direction,

wherein the memory plane is divided into a plurality of memory fingers by the plurality of second structures, and

the sub-plane includes a plurality of the memory fingers.

5. The semiconductor memory device according to claim 4, further comprising:

a second semiconductor layer connected to a lower end of the memory columnar body and extending in the third direction;

a source line contact connected at a lower end thereof to the second semiconductor layer and extending in the first direction; and

a source line provided above the source line contact and connected to the source line contact,

wherein the second structure includes the source line contact.

6. The semiconductor memory device according to claim 4, wherein

the memory plane comprises:

a first memory finger provided within the sub-plane; and

a second memory finger provided at a boundary of two of the sub-planes adjacent in the third direction,

the first memory finger is a memory finger recording user data, and

the second memory finger is a dummy finger not recording user data.

7. The semiconductor memory device according to claim 6, wherein

the memory plane further comprises a third memory finger provided between the first memory finger and the second memory finger, and

the third memory finger is a dummy finger not recording user data.

8. The semiconductor memory device according to claim 1, wherein

each of the memory columnar body and the first structure further comprises a third insulating film having a side surface covered by the first semiconductor layer.

9. The semiconductor memory device according to claim 1, wherein

the first semiconductor layer extends in the first direction, and

each of the memory columnar body and the first structure further comprises a third semiconductor layer provided at a lower end of the first semiconductor layer.

10. The semiconductor memory device according to claim 1, wherein

a width in the third direction of the first structure is larger than a width in the third direction of the memory columnar body.

11. A method of manufacturing a semiconductor memory device, comprising:

stacking a plurality of first films and inter-layer insulating films in a first direction above a substrate to form a stacked body extending in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction;

forming a first opening in the stacked body, the first opening penetrating the stacked body;

forming a second opening in the stacked body, the second opening extending in the second direction and dividing the stacked body in the third direction;

sequentially forming a memory insulating film and an amorphous semiconductor layer on inner walls of the first opening and the second opening;

performing heat treatment on the amorphous semiconductor layer and reforming a crystalline structure of the amorphous semiconductor layer to form a first semiconductor layer; and

forming a first conductive film facing the first semiconductor layer via the memory insulating film.

12. The method of manufacturing a semiconductor memory device according to claim 11, further comprising:

when forming the first conductive film,

forming a third opening in the stacked body, the third opening extending in the second direction;

removing the first film via the third opening; and

forming the first conductive film between a plurality of the inter-layer insulating films via the third opening.

13. The method of manufacturing a semiconductor memory device according to claim 11, wherein

the first films are conductive films, and

the first conductive films are formed by forming a third opening in the stacked body, the third opening extending in the second direction.

14. The method of manufacturing a semiconductor memory device according to claim 11, wherein

the second opening is formed in a batch along with the first opening.

15. The method of manufacturing a semiconductor memory device according to claim 11, wherein

a plurality of the second openings are formed at first intervals in the third direction.

16. The method of manufacturing a semiconductor memory device according to claim 11, wherein

a plurality of the second openings are formed at first intervals in the third direction, and

a plurality of third openings are formed at second intervals smaller than the first intervals in the third direction after performing the heat treatment, the third opening extending in the second direction.