REGULATED VOLTAGE SYSTEMS AND METHODS USING INTRINSICALLY VARIED PROCESS CHARACTERISTICS

• US 20180026527A1
• Filed: 07/25/2016
• Published: 01/25/2018
• Est. Priority Date: 07/25/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tai, Chia Liang
• Granted Patent: US 10,637,351 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/16576 comparing DC or AC voltage with one threshold G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/072 adapted to generate an output voltage whose value is lower than the input voltage

Abstract

A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Claims

1. A system, comprising:

a detector circuit having a plurality of detectors, wherein each of the plurality of detectors has a predetermined threshold voltage; and

a multi-cell charge/discharge circuit having a plurality of charge pumps, wherein each of the charge pumps is configured to generate a predetermined charge, and wherein each of the charge pumps is associated with one of the plurality of detectors of the detector circuit.

2. The system of claim 1, wherein each of the plurality of pumping cells are shunted together.

3. The system of claim 1, wherein each of the charge pumps is configured to generate an identical charge.

4. The system of claim 1, wherein the detector circuit is configured to generate an n-bit output to activate one or more of the charge pumps based on a comparison between a reference voltage and an output voltage of the multi-cell charge/discharge circuit.

5. The system of claim 4, wherein n is a number of charge pumps in the multi-cell charge/discharge circuit.

6. The system of claim 4, wherein the detector sequentially activates one or more charge pumps at each of the predetermined threshold voltages.

7. The system of claim 1, wherein each of the predetermined threshold voltages is determined by one or more intrinsic process variations of each of the plurality of detectors.

8. A detector circuit, comprising:

a current comparator configured to generate an output based on a comparison of a reference voltage to a trigger voltage; and

a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variation of the current comparator.

9. The detector circuit of claim 8, wherein the compensation circuit includes at least one compensation transistor configured to compensate for variations in a constant transconductance bias current of the current comparator.

10. The detector circuit of claim 9, wherein the at least one compensation transistor comprises an NMOS transistor having a gate coupled to an output of a current source of the current comparator, a source coupled to a pass-gate transistor of the current comparator, and a drain coupled to ground.

11. The detector circuit of claim 8, wherein the compensation circuit includes at least one compensation transistor configured to compensate for process variations in one or more of a width, a length, or a threshold voltage of at least one transistor of the current comparator.

12. The detector circuit of claim 11, wherein the at least one compensation transistor comprises a PMOS transistor having a gate coupled to an output of a two-NMOS transistor comparison circuit, a source coupled to pass-gate transistor of the current comparator, and a drain coupled to ground.

13. The detector circuit of claim 8, wherein the current comparator comprises:

a positive reference system including a PMOS current source and a PMOS pass-gate;

a negative reference system including an NMOS current source and an NMOS pass-gate; and

a transistor coupled between a pump output voltage input and at least one of the PMOS pass-gate and the NMOS pass-gate.

14. The detector circuit of claim 13, wherein the positive reference system is configured to generate an output signal for at least one charge pump during a positive phase of a load current, and wherein the negative reference system is configured to generate the output signal for the at least one charge pump during a negative phase of the load current.

15. A regulator system, comprising:

a plurality of detectors each comprising;

a current comparator configured to generate an output by comparing a reference voltage to a trigger voltage, wherein the trigger voltage is determined by one or more process variations of the current comparator; and

a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variations of the current comparator; and

a plurality of charge pumps each associated with at least one of the plurality of detectors, wherein each of the charge pumps is configured to generate a predetermined charge.

16. The regulated voltage system of claim 15, wherein the predetermined charge generated by each of the charge pumps is equal.

17. The regulated voltage system of claim 15, wherein the compensation circuit includes at least one compensation transistor configured to compensate for variations in a constant transconductance bias current of the current comparator.

18. The regulated voltage system of claim 17, wherein the at least one compensation transistor comprises an NMOS transistor having a gate coupled to an output of a current source of the current comparator, a source coupled to a pass-gate transistor of the current comparator, and a drain coupled to ground.

19. The regulated voltage system of claim 15, wherein the compensation circuit includes at least one compensation transistor configured to compensate for process variations in one or more of a width, a length, or a threshold voltage of at least one transistor of the current comparator.

20. The regulated voltage system of claim 19, wherein the at least one compensation transistor comprises a PMOS transistor having a gate coupled to an output of a two-NMOS transistor comparison circuit, a source coupled to pass-gate transistor of the current comparator, and a drain coupled to ground.