SYSTEM AND METHOD FOR ADJUSTING DEVICE PERFORMANCE BASED ON SENSED HOST CURRENT SOURCING CAPABILITY

• US 20180032122A1
• Filed: 07/29/2016
• Published: 02/01/2018
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Agrawal, Ankur
• Granted Patent: US 10,061,378 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A system and method is disclosed for an electronic device, such as a non-volatile memory associated with a host, to determine a current sourcing capability of the host and to adjust performance characteristics of the electronic device based on the determined current sourcing capability. The system may include an input current source testing circuit, device function circuitry and a controller configured to determine a current sourcing capability of a host with the input current source testing circuit, select a device performance parameter associated with the determined current sourcing capability and operate the device function circuitry according to the device performance parameter until detecting a power-off event. The method may include the electronic device reducing a resistance presented to the host to a plurality of predetermined resistance levels to determine the current sourcing capability of the host and utilizing the results of the determination to select associated device performance parameters.

Claims

1. A method for adjusting device performance parameters for a device, the method comprising:

detecting a connection with a host;

generating a busy indicator at the device identifiable by the host as representing that the device is in a busy state;

determining a current sourcing capability of the host via the connection; and

selecting a device performance parameter from a plurality of device performance parameters based on the determined current sourcing capability.

2. The method of claim 1, wherein detecting the connection comprises detecting a predetermined initial power-up voltage from the host.

3. The method of claim 2, wherein generating the busy indication comprises transmitting the busy indicator to the host over the connection.

4. The method of claim 1, wherein determining the current sourcing capability comprises changing a resistance presented to the host over the connection from a default resistance and subsequently measuring a voltage supply level from the host.

5. The method of claim 4, wherein changing the resistance comprises:

switching the resistance from the default resistance to a first resistance lower than the default resistance; and

wherein when the subsequently measured voltage supply remains within a predetermined voltage range, the memory system selects a higher current consumption device performance parameter.

6. The method of claim 5, wherein the device is a memory system and the higher current consumption device performance parameter comprises an increased number of concurrently active non-volatile memory die over a default number of concurrently active non-volatile memory die.

7. The method of claim 4, further comprising maintaining the selected device performance parameter until a power-off event is detected.

8. An electronic device removably attachable to a host, the electronic device comprising:

an input current source testing circuit;

device function circuitry; and

a controller in communication with the input current source testing circuit and the device function circuitry, the controller configured to;

upon detection of an initial power-on voltage from the host, determine a current sourcing capability of the host at a plurality of current sourcing levels with the input current source testing circuit;

select a device performance parameter for the device function circuitry associated with the determined current sourcing capability from a plurality of device performance parameters; and

operate the device function circuitry according to the device performance parameter until detecting a power-off event.

9. The electronic device of claim 8, wherein the input current source testing circuit comprises a plurality of processor selectable resistance paths.

10. The electronic device of claim 9, wherein the plurality of processor selectable resistance paths are arranged for individual selection of only one of the plurality of resistance paths at any one time, wherein each of the plurality of resistance paths is a different resistance than each other of the resistance paths.

11. The electronic device of claim 9, wherein the plurality of processor selectable resistance paths are arranged for selection of one of the plurality of resistance paths or selection of multiple ones of the plurality of resistance paths in parallel at any one time.

12. The electronic device of claim 9, wherein each of the plurality of resistance paths comprise a resistor.

13. The electronic device of claim 9, wherein to determine the current sourcing capability of the host at the plurality of current sourcing levels, the controller is configured to alter an input resistance presented to the host via the input current source testing circuit until an input voltage from the host falls below a predetermined threshold.

14. The electronic device of claim 13, wherein the electronic device comprises a non-volatile memory system.

15. The electronic device of claim 13, wherein the controller is configured to alter the input resistance by reducing the input resistance presented to the host via the input current source testing circuit.

16. The electronic device of claim 8, wherein the electronic device comprises a non-volatile memory system, and the device function circuitry comprises a plurality of non-volatile memory die.

17. The electronic device of claim 16, wherein the device performance parameters comprise a number of concurrently active non-volatile memory die of the plurality of non-volatile memory die.

18. The electronic device of claim 16, wherein at least one of the plurality of non-volatile memory die comprises a silicon substrate and a plurality of memory cells forming a monolithic three-dimensional structure, wherein at least one portion of the memory cells is vertically disposed with respect to the silicon substrate.

19. An electronic device removably attachable to a host via a host connection, the electronic device comprising:

device function circuitry; and

means for determining a current sourcing capability of the host via the connection; and

means for selecting a device performance parameter from a plurality of device performance parameters based on the determined current sourcing capability and for operating the device function circuitry according to the selected device performance parameter.

20. The electronic device of claim 19, wherein the electronic device comprises a non-volatile memory system, and the device function circuitry comprises a plurality of non-volatile memory die.