PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS

• US 20180032312A1
• Filed: 07/29/2016
• Published: 02/01/2018
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Hansen, Craig, Moussouris, John, Massalin, Alexia
• Granted Patent: US 10,120,649 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/5045 for multiple operands
• CPC Class Codes: G06F 7/523 Multiplying only
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.

Claims

1. A processor for multiplying each one of a plurality n of multiplier operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b with each one of a plurality n of multiplicand operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b, the processor comprising:

a register file having a bit width of r bits;

an array of multipliers arranged in rows and columns, each column coupled to receive one multiplier operand, each row coupled to receive one multiplicand operand, whereby each multiplier receives a multiplier operand and a multiplicand operand and multiplies them together to provide a plurality n² of multiplication results having an aggregate bit width greater than r bits;

an array of adders arranged in rows and columns, each adder being coupled to a corresponding multiplier;

an array of accumulators arranged in rows and columns, each accumulator being coupled to a corresponding adder; and

wherein the multiplication result from each multiplier is added to any previous multiplication result stored in the accumulator and provided to the corresponding accumulator and to thereby provide an accumulation result.

2. A processor as in claim 1 in which a single instruction causes the processor to perform multiplications of the operands and accumulations of the multiplications.

3. A processor as in claim 1 wherein the accumulator retains values in a redundant form.

4. A processor as in claim 1 further including an array of output stages, each output stage being coupled to the corresponding accumulator for storing the accumulation results before transfer of the accumulation results from the processor.

5. A processor as in claim 4 further comprising an array of switching circuits coupled between each accumulator and its corresponding output stage for controlling data provided to the output stage.

6. A processor as in claim 5 wherein the switching circuits enable data from another accumulator in the array to be provided to the output stage.

7. A processor as in claim 4 further comprising an array of additional data processing circuits arranged in rows and columns, the additional data processing circuits coupled between each accumulator and a corresponding output stage, the additional data processing circuits for performing further operations on data in the accumulators.

8. A processor as in claim 7 wherein the additional data processing circuits provide at least one of extraction of a portion of the data in the accumulators, rounding of the data in the accumulators, or application of a function of the data in the accumulators.

9. A processor as in claim 4 further comprising at least one data processing circuit coupled to the array to provide at least one of extraction of a portion of the data in the accumulators, rounding of the data in the accumulators, or application of a function of the data in the accumulators as that data from the accumulators is transferred out of the array.

10. A processor as in claim 9 wherein the at least one data processing circuit comprises a plurality of data processing circuits, each data processing circuit coupled to subset of less than all of the accumulators in the array.

11. In a processor for multiplying each one of a plurality n of multiplier operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b with each one of a plurality n of multiplicand operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b, a tile of the processor comprising:

a multiplier coupled to receive one of a plurality n of multiplier operands and one of a plurality n of multiplicand operands and multiply them together to provide a multiplication result having a bit width greater than r bits;

an adder coupled to the multiplier; and

an accumulator coupled to the adder; and

wherein the multiplication result from the multiplier is provided to the adder and added to any previous multiplication result stored in the accumulator to thereby provide an accumulation result.

12. A tile as in claim 11 further comprising an output stage coupled to the accumulator for storing the accumulation result.

13. A tile as in claim 12 further comprising a switching circuit coupled between the accumulator and the output stage for selecting data to be provided to the output stage.

14. A tile as in claim 13 wherein the switching circuit enables data from another tile to be provided to the output stage.

15. In a processor having an array of multipliers arranged in rows and columns, an array of accumulators arranged in rows and columns, and an array of adders arranged in rows and columns, each multiplier having an associated adder and an associated accumulator, the processor having a register file with a bit width of r bits, a method of performing an outer product of a vector multiplier operand and a vector multiplicand operand comprising:

loading a first multiplier operand and a first multiplicand operand into each of the multipliers, the multiplier at location [i, j] in the array receiving first multiplier operand i and first multiplicand operand j;

at each multiplier performing a multiplication of the first multiplier operand i and the first first multiplicand operand j to produce a first multiplication result i*j which is wider than r bits; and

providing the first multiplication result to the associated adder;

adding the first multiplication result to any previous multiplication result to provide an accumulated multiplication result to the associated accumulator.

16. A method as in claim 15 further comprising:

loading a second multiplier operand and a second multiplicand operand into each of the multipliers, the multiplier at location [i, j] in the array receiving second multiplier operand i and second multiplicand operand j;

at each multiplier performing a multiplication of the second multiplier operand i and the second multiplicand operand j to produce a second multiplication result i*j which is wider than r bits;

at each multiplier providing the second multiplication result to the associated adder;

at each multiplier providing the first multiplication result from the associated accumulator to the associated adder;

adding the second multiplication result to the first multiplication result to provide a new accumulation result; and

storing the new accumulation result in the associated accumulator.

17. A method as in claim 16 wherein a single instruction causes the processor to perform multiplications of the operands and accumulations of the multiplications.

18. A method as in claim 16 wherein the processor further includes an array of output stages, each output stage being coupled to an associated accumulator, and the method further comprises storing the new accumulation result in the output stage.

19. A method as in claim 16 further comprising an array of switching circuits coupled between each accumulator and its associated output stage for controlling data provided to the output stage.

20. A method as in claim 19 wherein the switching circuits enable data from another accumulator in the array to be provided to the output stage associated with a different accumulator.

21. A method as in claim 18 further comprising a step of at least one of:

(i) extraction of a portion of data in the accumulators, (ii) rounding of data in the accumulators, or (iii) application of a function to data in the accumulators.

22. A method as in claim 18 further comprising an array of additional data processing circuits arranged in rows and columns, the additional data processing circuits coupled between each accumulator and each output stage, the additional data processing circuits for performing further operations on data in the accumulators.

23. A method as in claim 22 wherein the additional data processing circuits perform at least one of extraction of a portion of data in the accumulators, rounding of data in the accumulators, or application of a function to data in the accumulators.