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PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS

  • US 20180032312A1
  • Filed: 07/29/2016
  • Published: 02/01/2018
  • Est. Priority Date: 07/29/2016
  • Status: Active Grant
First Claim
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1. A processor for multiplying each one of a plurality n of multiplier operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b with each one of a plurality n of multiplicand operands each having a bit width of b bits and having an aggregate width of r bits where r=n*b, the processor comprising:

  • a register file having a bit width of r bits;

    an array of multipliers arranged in rows and columns, each column coupled to receive one multiplier operand, each row coupled to receive one multiplicand operand, whereby each multiplier receives a multiplier operand and a multiplicand operand and multiplies them together to provide a plurality n2 of multiplication results having an aggregate bit width greater than r bits;

    an array of adders arranged in rows and columns, each adder being coupled to a corresponding multiplier;

    an array of accumulators arranged in rows and columns, each accumulator being coupled to a corresponding adder; and

    wherein the multiplication result from each multiplier is added to any previous multiplication result stored in the accumulator and provided to the corresponding accumulator and to thereby provide an accumulation result.

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