TRANSACTIONAL REGISTER FILE FOR A PROCESSOR

• US 20180032335A1
• Filed: 07/31/2016
• Published: 02/01/2018
• Est. Priority Date: 07/31/2016
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Smith, Aaron L., Gray, Jan S.
• Application Number:
  US15/224,593
• Publication Number:
  US 20180032335A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

Technology related to register files for block-based processor architectures is disclosed. In one example of the disclosed technology, a processor core including a transactional register file and an execution unit can be used to execute an instruction block. The transactional register file can include a plurality of registers, where each register includes a previous value field and a next value field. The previous value field can be updated when a register-write message is received and the processor core is in a first state. The next value field can be updated when a register-write message is received and the processor core is in a second state. The execution unit can execute instructions of the instruction block. The execution unit can be configured to read register values from the previous value field and to cause register-write messages to be transmitted from the processor core when executing instructions that write to the registers.

Claims

1. A block-based processor core for executing an instruction block, the processor core comprising:

a transactional register file comprising a plurality of registers, each register including a previous value field and a next value field, the previous value field for storing a value corresponding to a state before execution of the instruction block on the processor core, the next value field for storing a value corresponding to a state after execution of the instruction block on the processor core, the next value field being updated when a register-write message is received and the processor core is executing non-speculatively, and the previous value field being updated when a register-write message is received and the processor core is executing speculatively; and

an execution unit configured to execute instructions of the instruction block, the execution unit configured to read register values from the previous value field of the transactional register file and to cause register-write messages to be transmitted from the processor core when the instructions of the instruction block write to the registers.

2. The processor core of claim 1, wherein the transactional register file further comprises a pending state for each register of the plurality of registers, and the pending state is asserted in response to receiving a write-mask message indicating the register is written by an instruction of an instruction block earlier in program order than the instruction block being executed on the processor core.

3. The processor core of claim 2, further comprising:

instruction scheduler logic configured to issue the instructions of the instruction block to the execution unit in a dataflow order based at least in part on the pending state for each register of the transactional register file.

4. The processor core of claim 2, further comprising:

decode logic configured to determine registers to be written by the instructions of the instruction block and to cause a write-mask message to be transmitted from the processor core, the write-mask message indicating at least the registers to be written by the instructions of the instruction block.

5. The processor core of claim 4, wherein the write-mask message indicates the registers to be written by the instructions of the instruction block and registers having an asserted pending state.

6. The processor core of claim 1, wherein the execution unit is further configured to detect an abort condition of an instruction of the instruction block and to cause a pause message to be transmitted from the processor core when the abort condition is detected.

7. The processor core of claim 6, further comprising:

abort management logic configured to determine all registers of the transactional register file speculatively written by the instructions of the instruction block and to perform a rollback action that restores a value of each register speculatively written by the instructions of the instruction block.

8. The processor core of claim 7, wherein the abort management logic is further configured to cause an abort message to be transmitted from the processor core after the abort condition is detected and after all of the register-write messages for each register speculatively written by the instructions of the instruction block are transmitted from the processor core.

9. The processor core of claim 1, wherein the execution unit is further configured to cause a register-write message to be transmitted from the processor core in response to a nullify instruction being executed, the nullify instruction indicating a register that is not written by the instruction block, the register-write message including the value stored in the previous value field for the register that is not written by the instruction block.

10. A method of executing an instruction block, the method comprising:

receiving a first register-write message at a processor core, the first register-write message comprising a register value;

selecting a previous register value field or a next register value field of an entry of a transactional register file to update based on a state of the processor core; and

updating the selected register value field of the entry of the transactional register file with the register value.

11. The method of claim 10, wherein the next register value field is selected for updating when the state of the processor core is a non-speculative execution state.

12. The method of claim 10, wherein the previous register value field is selected for updating when the state of the processor core is not a non-speculative execution state.

13. The method of claim 10, further comprising:

receiving a write-mask message at the processor core, the write-mask message indicating the registers of the transactional register file to be written by one or more instruction blocks earlier in program order than the instruction block; and

issuing the instructions of the instruction block for execution in a dataflow order based at least in part on the received write-mask message.

14. The method of claim 10, further comprising:

executing an instruction of the instruction block to generate a result of the instruction; and

transmitting a second register-write message from the processor core in response to executing the instruction when the instruction specifies a register of the transactional register file to write, the second register-write message including a register identifier of the register and the result of the instruction.

15. The method of claim 14, further comprising:

causing a third register-write message to be transmitted from the processor core during an abort state of the processor core, the third register-write message including the register identifier of the register and the value stored in the previous value field of the register.

16. The method of claim 10, further comprising:

executing a nullify instruction of the instruction block, the nullify instruction specifying that a register of the transactional register file is not written by the instruction block, thereby specifying the register is a nullified register; and

transmitting a second register-write message from the processor core in response to executing the nullify instruction, the second register-write message including the value stored in the previous register value field for the nullified register.

17. A block-based processor core for executing instructions of an instruction block, the processor core comprising:

a communication system configured to receive and transmit messages;

a transactional register file comprising a plurality of registers, each register including a previous value field and a next value field, the previous value field being configured to be updated based on the communication system receiving a register-write message when the processor core is in a first operational state, and the next value field being configured to be updated based on the communication system receiving a register-write message when the processor core is in a second operational state different from the first operational state; and

execution logic configured to execute the instructions of the instruction block, the execution logic being configured to read register values from the previous value field of the transactional register file and to cause register-write messages to be transmitted by the communication system when the instructions of the instruction block write to the registers.

18. The processor core of claim 17, wherein the communication system configured to receive messages from an upstream processor core and to transmit messages to a downstream processor core.

19. The processor core of claim 17, wherein the operational state of the processor core is maintained by a state machine configured to track the operational state of the processor core based on the messages received by the communication system and results of executing the instructions of the instruction block.

20. The processor core of claim 17, further comprising:

abort management logic configured to;

detect an abort condition based on the communication system receiving an abort message; and

cause register-write messages to be transmitted by the communication system for each register speculatively written by the executed instructions of the instruction block.