SYSTEM AND METHOD FOR CONTROLLING CACHE FLUSH SIZE

• US 20180032439A1
• Filed: 07/28/2016
• Published: 02/01/2018
• Est. Priority Date: 07/28/2016
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Jenne, John E., Berke, Stuart Allen, Sankaranarayanan, Vadhiraj
• Granted Patent: US 10,474,583 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/60 Details of cache memory

Abstract

An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Claims

1. A method for controlling cache flush size in an information handling system, comprising:

setting a threshold value for modified cache lines in a cache;

writing to a cache line in the cache;

determining whether or not the writing causes the cache line to transition to a modified state;

in response to determining that that the writing causes the cache line to transition to the modified state;

incrementing a count of modified cache lines in the cache;

determining, dependent on the incremented count, whether or not the threshold value for modified cache lines in the cache is exceeded; and

flushing one or more modified cache lines in the cache to persistent memory, in response to determining that the threshold value for modified cache lines in the cache is exceeded.

2. The method of claim 1, wherein flushing one or more modified cache lines in the cache to the persistent memory comprises flushing all modified cache lines in the cache to the persistent memory.

3. The method of claim 1, wherein:

flushing one or more modified cache lines in the cache to the persistent memory comprises flushing a number of modified cache lines in the cache to the persistent memory that is sufficient to reduce the modified cache lines in the cache below the threshold value for modified cache lines in the cache; and

the one or more modified cache selected for flushing is dependent on an applicable cache replacement policy.

4. The method of claim 1, wherein the threshold value represents a maximum allowed number of cache lines in the cache that are in the modified state.

5. The method of claim 1, wherein:

the threshold value represents a maximum allowed percentage of cache lines in the cache that are in the modified state; and

determining whether or not the threshold value for modified cache lines in the cache is exceeded comprises calculating, dependent on the incremented count, the percentage of cache lines in the cache that are in the modified state.

6. The method of claim 1, wherein:

the threshold value represents a maximum allowed number of cache lines in the cache that are in the modified state and that are targeted to the persistent memory;

the count of modified cache lines in the cache comprises a count of cache lines in the cache that are in the modified state and that are targeted to the persistent memory; and

flushing the one or more modified cache lines in the cache to the persistent memory comprises flushing to the persistent memory one or more modified cache lines in the cache that are targeted to persistent memory.

7. The method of claim 1, wherein flushing the one or more modified cache lines in the cache to the persistent memory comprises transitioning the one or more modified cache lines from the modified state to an exclusive state.

8. The method of claim 1, wherein flushing the one or more modified cache lines in the cache to the persistent memory comprises transitioning the one or more modified cache lines from the modified state to an invalid state.

9. The method of claim 1, wherein the threshold value is dependent on one or more of:

available hold-up energy in the system or an amount of time to flush the one or more modified cache lines to the persistent memory.

10. The method of claim 1, wherein setting the threshold value for modified cache lines in the cache comprises setting the threshold value to a fixed value during an initialization of the information handling system.

11. The method of claim 1, wherein:

setting the threshold value for modified cache lines in the cache comprises setting the threshold value to an initial threshold value; and

the method further comprises modifying the threshold value for modified cache lines in the cache during operation of the information handling system in response to an increase or decrease in hold-up energy.

12. An information handling system, comprising:

at least one cache; and

a cache controller comprising circuitry to;

store a threshold value for modified cache lines in a cache;

detect a write to a cache line in the cache;

determine whether or not the write causes the cache line to transition to a modified state;

in response to a determination that that the write causes the cache line to transition to the modified state;

increment a count of modified cache lines in the cache;

determine, dependent on the incremented count, whether or not the threshold value is exceeded;

flush one or more modified cache lines in the cache to persistent memory, in response to a determination that the threshold value is exceeded; and

elide a flush of the one or more modified cache lines in the cache to persistent memory, in response to a determination that the threshold value is not exceeded.

13. The information handling system of claim 12, wherein to flush the one or more modified cache lines in the cache to the persistent memory, the cache controller comprises circuitry to:

flush all modified cache lines in the cache to the persistent memory;

or

flush, dependent on an applicable cache replacement policy, a number of modified cache lines in the cache to the persistent memory that is sufficient to reduce the modified cache lines in the cache below the threshold value for modified cache lines in the cache.

14. The information handling system of claim 12, wherein the threshold value is dependent on one or more of:

available hold-up energy in the system or an amount of time to flush the one or more modified cache lines to the persistent memory.

15. The information handling system of claim 12, wherein the threshold value represents a maximum allowed number of cache lines in the cache that are in the modified state or a maximum allowed percentage of cache lines in the cache that are in the modified state.

16. The information handling system of claim 12, wherein the threshold value for modified cache lines in the cache is configurable during an initialization of the information handling system or during operation of the information handling system.

17. The information handling system of claim 12, wherein:

the information handling system further comprises a page table including a plurality of entries, each of which includes a first field whose value indicates whether or not a respective cache line is targeted to persistent memory and a second field whose value indicates whether or not the respective cache line has been modified;

the threshold value represents a maximum allowed number of cache lines in the cache that are in the modified state and that are targeted to the persistent memory;

the cache controller further comprises circuitry to;

determine, dependent on its respective page table entry, whether or not the written cache line is targeted to persistent memory; and

increment the count of modified cache lines in the cache in response to a determination that the written cache line is targeted to persistent memory;

to flush the one or more modified cache lines in the cache to persistent memory, the cache controller further comprises circuitry to flush to the persistent memory only cache lines in the cache that are in the modified state and that are targeted to the persistent memory.

18. A cache controller, comprising circuitry to:

store a threshold value for modified cache lines in a cache;

detect a write to a cache line in the cache;

determine whether or not the write causes the cache line to transition to a modified state;

in response to a determination that that the write causes the cache line to transition to the modified state;

increment a count of modified cache lines in the cache;

determine, dependent on the incremented count, whether or not the threshold value is exceeded;

flush one or more modified cache lines in the cache to persistent memory, in response to a determination that the threshold value is exceeded; and

elide a flush of the one or more modified cache lines in the cache to persistent memory, in response to a determination that the threshold value is not exceeded.

19. The cache controller of claim 18, wherein to flush the one or more modified cache lines in the cache to the persistent memory, the cache controller comprises circuitry to:

flush all modified cache lines in the cache to the persistent memory;

or

flush, dependent on an applicable cache replacement policy, a number of modified cache lines in the cache to the persistent memory that is sufficient to reduce the modified cache lines in the cache below the threshold value for modified cache lines in the cache.

20. The cache controller of claim 18, wherein the threshold value is dependent on one or more of:

available hold-up energy in the system or an amount of time to flush the one or more modified cache lines to the persistent memory.