Processor For Enhancing Computer Security

• US 20180032729A1
• Filed: 10/10/2017
• Published: 02/01/2018
• Est. Priority Date: 03/07/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,489,590 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 18/00 Pattern recognition
• CPC Class Codes: G06F 21/564 by virus signature recognition
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06V 10/955 using specific electronic processors
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

Claims

1. A processor for enhancing computer security, comprising:

an input for transferring at least a computer data;

a semiconductor substrate having transistors thereon;

a plurality of storage-processing units (SPU), each of said SPUs comprising a pattern-processing circuit and at least a three-dimensional memory (3D-M) array, wherein

said 3D-M array is stacked above said pattern-processing circuit and stores at least a virus pattern;

said pattern-processing circuit is formed on said semiconductor substrate and performs pattern matching or pattern recognition on said computer data against said virus pattern;

said 3D-M array and said pattern-processing circuit are communicatively coupled by a plurality of contact vias.

2. The processor according to claim 1, further comprising first and second SPUs formed side-by-side.

3. The processor according to claim 2, wherein both of said first and second SPUs are communicatively coupled with said input.

4. The processor according to claim 2, further comprising an output for transferring at least a result of said pattern matching or pattern recognition.

5. The processor according to claim 4, wherein both of said first and second SPUs are communicatively coupled with said output.

6. The processor according to claim 1, wherein said 3D-M array is three-dimensional writable memory (3D-W) array.

7. The processor according to claim 6, wherein said 3D-W array is a three-dimensional one-time-programmable memory (3D-OTP) array.

8. The processor according to claim 6, wherein said 3D-W array is a three-dimensional multiple-time-programmable memory (3D-MTP) array.

9. The processor according to claim 1, wherein said 3D-M array is three-dimensional printed memory (3D-P) array.

10. The processor according to claim 9, wherein said 3D-P array is a three-dimensional mask-programmed read-only memory (3D-MPROM) array.

11. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a text-matching circuit.

12. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a code-matching circuit.

13. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a comparator.

14. The processor according to claim 13, wherein said comparator comprises XOR circuits.

15. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a content-addressable memory (CAM).

16. The processor according to claim 1, wherein said pattern-processing circuit comprises at least a finite-state automata (FSA) circuit.

17. The processor according to claim 16, wherein said FAS circuit comprises at least a non-deterministic FSA (NFA) circuit.

18. The processor according to claim 16, wherein said FAS circuit comprises at least a deterministic FSA (DFA) circuit.

19. The processor according to claim 1, wherein said 3D-M array at least partially covers said pattern-processing circuit.

20. The processor according to claim 1, wherein said pattern-processing circuit is covered by at least two 3D-M arrays.