MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20180033492A1
• Filed: 01/05/2017
• Published: 02/01/2018
• Est. Priority Date: 07/28/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SEO, Ji Hyun
• Granted Patent: US 9,972,399 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

Claims

1. A memory device comprising:

a plurality of memory cells stacked along pillar vertical'"'"'a substrate;

a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells; and

a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

2. The memory device according to claim 1, wherein the control logic is configured to control the peripheral circuit so that:

when memory cells located in a pillar region in which a width of the pillar is smaller than a reference width are verified, a second pass voltage higher than a first pass voltage is applied to unselected word lines adjacent to the selected word line, among the unselected word lines and the first pass voltage is applied to remaining unselected word lines.

3. The memory device according to claim 1, wherein the pillar is divided into a plurality of pillar regions depending on a width of the pillar.

4. The memory device according to claim 3, wherein the control logic is configured to control the peripheral circuit so that the pass voltage is adjusted depending on a pillar region in which the selected word line is included, among the plurality of pillar regions.

5. The memory device according to claim 4, wherein the control logic is configured to control the peripheral circuit so that, as the width of the pillar in which the selected word line is included becomes smaller, the pass voltage is gradually increased.

6. The memory device according to claim 1, wherein the pillar is formed in an “

I”

-shape or a “

U”

-shape over the substrate.

7. The memory device according to claim 1, wherein:

the pillar is formed in a single-stack structure implemented as a single layered structure, or in a multi-stack structure in which one or more stacks are piled up.

8. The memory device according to claim 7, wherein, when the pillar is formed in the single-stack structure, the control logic is configured to control the peripheral circuit so that:

when memory cells located in an upper portion of the pillar are verified, a first pass voltage is applied to all the unselected word lines, and

when memory cells located in a lower portion of the pillar are verified, a second pass voltage higher than the first pass voltage is applied to unselected word lines adjacent to the selected word line, among the unselected word lines, and the first pass voltage is applied to remaining unselected word lines.

9. The memory device according to claim 7, wherein, when the pillar is formed in the multi-stack structure, the control logic is configured to control the peripheral circuit so that the pass voltage applied to the unselected word lines is adjusted depending on the location of the selected word line and a sequence of a program operation, when the memory cells are verified.

10. The memory device according to claim 1, wherein the peripheral circuit comprises a voltage generation circuit configured to generate pass voltages having various levels under control of the control logic.

11. A method of operating a memory device, the method comprising:

setting a pillar region having a width smaller than a reference width;

determining whether a selected word line is included in the pillar region during a program operation;

When it is determined that the selected word line is not included in the pillar region, setting a first pass voltage, whereas when it is determined that the selected word line is included in the pillar region setting the first pass voltage and a second pass voltage higher than the first pass voltage;

programming memory cells coupled to the selected word line; and

verifying the memory cells by applying a verification voltage to the selected word line and applying either the first pass voltage or the first and second pass voltages to unselected word lines.

12. The method according to claim 11, wherein the first pass voltage is identical to a pass voltage used in a read operation.

13. The method according to claim 11, wherein the determining whether the selected word line is included in the pillar region is performed based on a row address included in an address received by the memory device.

14. The method according to claim 11, further comprising:

when it is determined that the selected word line is not included in the pillar region, applying the first pass voltage to all the unselected word lines.

15. The method according to claim 11, further comprising:

when it is determined that the selected word line is included in the pillar region, applying the second pass voltage to unselected word lines adjacent to the selected word line, among the unselected word lines, and applying the first pass voltage to remaining unselected word lines.

16. The method according to claim 15, wherein the second pass voltage is applied either to a unselected word line adjacent to the selected word line in an upward direction or to unselected word lines adjacent to the selected word line in upward and downward directions among the unselected word lines.

17. A method of operating a memory device, the method comprising:

defining a plurality of pillar regions depending on a width of pillar, wherein a plurality of memory cells are stacked along the pillar;

setting one or more pass voltages depending on a pillar region in which a selected word line is included, among the pillar regions;

programming memory cells coupled to the selected word line by applying a program voltage to the selected word line; and

verifying the memory cells by applying a verification voltage to the selected word line and selectively applying the pass voltages to unselected word lines.

18. The method according to claim 17, wherein, as the width of the pillar region in which the selected word line is included becomes smaller, a pass voltage that is applied to unselected word lines adjacent to the selected word line, among the unselected word lines, is increased.

19. The method according to claim 18, wherein a lowest voltage among the pass voltages is identical to a pass voltage used in a read operation.

20. The method according to claim 18, wherein the pass voltage that is applied to the unselected word lines adjacent to the selected word line is set to a voltage higher than a pass voltage that is applied to remaining unselected word lines except for the adjacent unselected word lines.