Measuring Internal Signals of an Integrated Circuit
First Claim
1. A device comprising:
- one or more blocks of circuitry;
a multiplexor having a plurality of inputs and an output;
a plurality of internal signal lines coupled from the one or more blocks of circuitry to respective ones of the plurality of inputs on the multiplexor;
a buffer with an input coupled to the output of the multiplexor and an output selectively coupled to a first external pin of the device; and
a direct signal line configured to selectively couple the output of the multiplexor directly to the first external pin of the device, such that the buffer is bypassed.
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Abstract
An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.
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Citations
12 Claims
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1. A device comprising:
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one or more blocks of circuitry; a multiplexor having a plurality of inputs and an output; a plurality of internal signal lines coupled from the one or more blocks of circuitry to respective ones of the plurality of inputs on the multiplexor; a buffer with an input coupled to the output of the multiplexor and an output selectively coupled to a first external pin of the device; and a direct signal line configured to selectively couple the output of the multiplexor directly to the first external pin of the device, such that the buffer is bypassed. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit comprising:
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functional logic having a plurality of internal signal lines; and test logic with a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit (IC), in which the test logic includes a buffer, and in which the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification