BINARY NEURAL NETWORKS ON PROGAMMABLE INTEGRATED CIRCUITS

• US 20180039886A1
• Filed: 08/05/2016
• Published: 02/08/2018
• Est. Priority Date: 08/05/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Umuroglu, Yaman, Blott, Michaela
• Granted Patent: US 10,089,577 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/0495 Quantised networks; Sparse networks; Compressed networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

Claims

1. A circuit of a neural network implemented in an integrated circuit (IC), comprising:

a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including;

a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights;

a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and

a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values;

wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

2. The circuit of claim 1, wherein the first logic signals input to the logic circuit of each of the hardware neurons is the plurality of inputs to the layer.

3. The circuit of claim 1, wherein the layer is configured to receive a plurality of weight signals supplying the plurality of weights, and wherein the logic circuit in each of the hardware neurons is an XNOR circuit.

4. The circuit of claim 1, wherein the logic circuit in at least a portion of the hardware neurons is either a pass circuit or an inverter based on a fixed value for each of the plurality of weights.

5. The circuit of claim 1, wherein the neural network comprises a plurality of layers, and wherein the circuit further comprises:

a control circuit configured to map each of the plurality of layers to the layer of hardware neurons in sequence over time.

6. The circuit of claim 1, further comprising:

a control circuit configured to supply each of a plurality of sets of input data to the plurality of inputs of the layer in sequence over time.

7. The circuit of claim 1, further comprising:

a control circuit configured to supply each of a plurality of sets of weights as the plurality of weights of the layer in sequence over time.

8. The circuit of claim 1, wherein the layer of hardware neurons is a first layer of hardware neurons, wherein the plurality of inputs, the plurality of outputs, the plurality of weights, and the plurality of threshold values are a first plurality of inputs, a first plurality of outputs, a first plurality of weights, and a first plurality of threshold values, respectively, and wherein the circuit further comprises:

a second layer of hardware neurons, the second layer including a second plurality of inputs, a second plurality of outputs, a second plurality of weights, and a second plurality of threshold values;

wherein the second plurality of inputs of the second layer is the first plurality of outputs of the first layer.

9. The circuit of claim 8, further comprising:

memory circuitry disposed between the first plurality of outputs of the first layer and the second plurality of inputs of the second layer.

10. A method of implementing a neural network in an integrated circuit (IC), comprising:

implementing a layer of hardware neurons in the IC, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values;

at each of the plurality of neurons;

receiving first logic signals from at least a portion of the plurality of inputs and supplying second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights;

receiving the second logic signals and supplying a count signal indicative of the number of the second logic signals having a predefined logic state; and

receiving the count signal and supplying a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values.

11. The method of claim 10, wherein the first logic signals input to each of the hardware neurons is the plurality of inputs to the layer.

12. The method of claim 10, wherein the layer is configured to receive a plurality of weight signals supplying the plurality of weights, and wherein each of the hardware neurons includes an XNOR circuit.

13. The method of claim 10, wherein at least a portion of the hardware neurons includes either a pass circuit or an inverter based on a fixed value for each of the plurality of weights.

14. The method of claim 10, wherein the neural network comprises a plurality of layers, and the method further comprises:

mapping each of the plurality of layers to the layer of hardware neurons in sequence over time.

15. The method of claim 10, further comprising:

supplying each of a plurality of sets of input data to the plurality of inputs of the layer in sequence over time.

16. The method of claim 10, further comprising:

supplying each of a plurality of sets of weights as the plurality of weights of the layer in sequence over time.

17. The method of claim 10, wherein the layer of hardware neurons is a first layer of hardware neurons, wherein the plurality of inputs, the plurality of outputs, the plurality of weights, and the plurality of threshold values are a first plurality of inputs, a first plurality of outputs, a first plurality of weights, and a first plurality of threshold values, respectively, and wherein the method further comprises:

implementing a second layer of hardware neurons, the second layer including a second plurality of inputs, a second plurality of outputs, a second plurality of weights, and a second plurality of threshold values;

wherein the second plurality of inputs of the second layer is the first plurality of outputs of the first layer.

18. The method of claim 17, further comprising:

memory circuitry disposed between the first plurality of outputs of the first layer and the second plurality of inputs of the second layer.

19. A programmable integrated circuit (IC), comprising:

a programmable fabric configured to implement;

a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including;

a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights;

a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and

a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values;

wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

20. The programmable IC of claim 19, wherein the layer is configured to receive a plurality of weight signals supplying the plurality of weights, and wherein the logic circuit in each of the hardware neurons is an XNOR circuit.