APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
First Claim
1. An apparatus, comprising:
- a memory cell including;
a memory element; and
a selector device electrically coupled to the memory element;
a first memory access line coupled to the memory cell;
a second memory access line coupled to the memory cell;
a first access line driver coupled to the first memory access line; and
a second access line driver coupled to the second memory access line,wherein the first and second access line drivers are configured to;
provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell,provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell,provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, andprovide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell.
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Accused Products
Abstract
Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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Citations
40 Claims
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1. An apparatus, comprising:
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a memory cell including; a memory element; and a selector device electrically coupled to the memory element; a first memory access line coupled to the memory cell; a second memory access line coupled to the memory cell; a first access line driver coupled to the first memory access line; and a second access line driver coupled to the second memory access line, wherein the first and second access line drivers are configured to; provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell, provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell, provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, and provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus, comprising:
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a memory cell configured to store multiple bits of data, wherein the multiple bits of data correspond to logic states of the memory cell; a first memory access line coupled to the memory cell; and a second memory access line coupled to the memory cell, wherein at least one of the multiple bits of data is determined by a magnitude of a current applied across the memory cell during a write pulse, and wherein at least one of the multiple bits of data is determined by a polarity of a voltage applied across the memory cell during the write pulse. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method, comprising:
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selecting a voltage of a write pulse; selecting a polarity of the write pulse; applying the write pulse having the voltage and polarity across a memory cell, wherein the write pulse writes a logic state to the memory cell, wherein the logic state is based, at least in part, on the voltage and polarity of the write pulse. - View Dependent Claims (25, 26, 27, 28, 29)
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30. A method, comprising:
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applying a read pulse having a first polarity to a memory cell, wherein a logic state of a plurality of logic states is written to the memory cell, wherein the logic state is based, at least in part, on a voltage and a polarity of a write pulse applied across the memory cell; sensing a current through the memory cell responsive to the read pulse; and determining the logic state of the plurality of logic states, based on the current through the memory cell. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification