APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME

• US 20180040370A1
• Filed: 08/08/2016
• Published: 02/08/2018
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tortorelli, Innocenzo, Meyer, Russell L., Pirovano, Agostino, Redaelli, Andrea, Fratin, Lorenzo, Pellizzer, Fabio
• Granted Patent: US 10,446,226 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/0052 Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode

Abstract

Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Claims

1. An apparatus, comprising:

a memory cell including;

a memory element; and

a selector device electrically coupled to the memory element;

a first memory access line coupled to the memory cell;

a second memory access line coupled to the memory cell;

a first access line driver coupled to the first memory access line; and

a second access line driver coupled to the second memory access line,

wherein the first and second access line drivers are configured to;

provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell,

provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell,

provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, and

provide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell.

2. The apparatus of claim 1, wherein, during a read operation on the memory cell, the memory cell exhibits a threshold voltage, wherein the threshold voltage is dependent on a logic state written to the memory cell.

3. The apparatus of claim 1, wherein the first, second, third, and fourth logic states correspond to values of a first bit and a second bit of data stored in the memory cell.

4. The apparatus of claim 3, wherein the first bit is stored in the memory element and the second bit is stored in the selector device.

5. The apparatus of claim 4, wherein a value of the first bit is based, at least in part, on whether the first or second voltage was applied across the memory cell.

6. The apparatus of claim 4, wherein a value of the second bit is based, at least in part, on whether the first or second polarity was applied across the memory cell.

7. The apparatus of claim 1, wherein the memory cell comprises a chalcogenide material.

8. The apparatus of claim 1, wherein the memory cell comprises at least one of silicon (Si), selenium (Se), arsenic (As), and germanium (Ge).

9. The apparatus of claim 1, wherein the first and second voltages are equal magnitudes and the third and fourth voltages are equal magnitudes.

10. The apparatus of claim 1, wherein the third and fourth logic states correspond to a same logic state.

11. The apparatus of claim 1, wherein the first access line driver is configured to provide a negative voltage and the second access line driver is configured to provide a non-negative voltage to provide the first or third voltage having the first polarity.

12. The apparatus of claim 1, wherein the first access line driver is configured to provide a first non-negative voltage and the second access line driver is configured to provide a second non-negative voltage to provide the first or third voltage having the first polarity, wherein the second non-negative voltage is greater than the first non-negative voltage.

13. An apparatus, comprising:

a memory cell configured to store multiple bits of data, wherein the multiple bits of data correspond to logic states of the memory cell;

a first memory access line coupled to the memory cell; and

a second memory access line coupled to the memory cell,

wherein at least one of the multiple bits of data is determined by a magnitude of a current applied across the memory cell during a write pulse, and wherein at least one of the multiple bits of data is determined by a polarity of a voltage applied across the memory cell during the write pulse.

14. The apparatus of claim 13, wherein the multiple bits of data are stored in different physical locations in the memory cell.

15. The apparatus of claim 13, wherein the memory cell includes a memory element and a selector device coupled to the memory element.

16. The apparatus of claim 15, wherein the at least one of the multiple bits of data determined by the polarity of the voltage are stored in the selector device.

17. The apparatus of claim 15, wherein the at least one of the multiple bits of data determined by the magnitude of the current are stored in the memory element.

18. The apparatus of claim 13, wherein the first memory access line is configured to provide a first non-negative voltage and the second memory access line is configured to provide a second non-negative voltage to provide the write pulse having the first polarity, wherein the second non-negative voltage is greater than the first non-negative voltage.

19. The apparatus of claim 13, wherein the magnitude of the current is one of a plurality of magnitudes, wherein a crystalline state of a phase change material of the memory cell depends, at least in part, on the magnitude of the current, and wherein a logic state of the memory cell depends, at least in part, on the crystalline state of the phase change material.

20. The apparatus of claim 13, wherein the memory cell exhibits one of a plurality of threshold voltages responsive to a read operation, wherein the plurality of threshold voltages correspond to the logic states of the memory cell.

21. The apparatus of claim 13, further comprising a memory array including a plurality of memory cells and a plurality of memory access lines coupled to at least some of the plurality of memory cells,

wherein the memory cell is one of the plurality of memory cells and the first and second memory access lines are each one of the plurality of memory access lines.

22. The apparatus of claim 21, wherein the memory array is a two-dimensional (2D) array or a three-dimensional (3D) array.

23. The apparatus of claim 13 further comprising a sense amplifier coupled to the first memory access line or the second memory access line, the sense amplifier configured to sense a current through the memory cell responsive to a read operation.

24. A method, comprising:

selecting a voltage of a write pulse;

selecting a polarity of the write pulse;

applying the write pulse having the voltage and polarity across a memory cell, wherein the write pulse writes a logic state to the memory cell, wherein the logic state is based, at least in part, on the voltage and polarity of the write pulse.

25. The method of claim 24, wherein selecting the voltage corresponds to selecting a value of a first bit to be written to the memory cell.

26. The method of claim 24, wherein selecting the polarity corresponds to selecting a value of a second bit to be written to the memory cell.

27. The method of claim 24, wherein the voltage is one of two voltages and the polarity is one of two polarities, and the logic state is one of four logic states.

28. The method of claim 24, wherein the logic state is one of a plurality of logic states, wherein the plurality includes at least three logic states.

29. The method of claim 28, wherein the logic state of the memory cell corresponds to multiple bits, wherein the multiple bits of data are stored in different physical locations in the memory cell.

30. A method, comprising:

applying a read pulse having a first polarity to a memory cell, wherein a logic state of a plurality of logic states is written to the memory cell, wherein the logic state is based, at least in part, on a voltage and a polarity of a write pulse applied across the memory cell;

sensing a current through the memory cell responsive to the read pulse; and

determining the logic state of the plurality of logic states, based on the current through the memory cell.

31. The method of claim 30, wherein the current is sensed with a sense amplifier.

32. The method of claim 30, wherein the read pulse is a ramped voltage pulse.

33. The method of claim 32, wherein a voltage of the ramped voltage pulse is increased linearly.

34. The method of claim 32, wherein a voltage of the ramped voltage pulse is increased non-linearly.

35. The method of claim 32, wherein the logic state is determined based, at least in part, on a time when the current is sensed.

36. The method of claim 30, wherein the read pulse is a staircase voltage pulse, wherein the voltage staircase pulse includes at least two voltage levels.

37. The method of claim 36, wherein the logic state is determined based, at least in part, on a voltage level of the staircase voltage pulse when the current is sensed.

38. The method of claim 30, wherein the current is sensed responsive to a threshold event of the memory cell.

39. The method of claim 30, wherein a duration of the read pulse is between 1 nanosecond-1 microsecond.

40. The method of claim 30, further comprising rewriting the logic state to the memory cell after determining the logic state.