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APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME

  • US 20180040370A1
  • Filed: 08/08/2016
  • Published: 02/08/2018
  • Est. Priority Date: 08/08/2016
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory cell including;

    a memory element; and

    a selector device electrically coupled to the memory element;

    a first memory access line coupled to the memory cell;

    a second memory access line coupled to the memory cell;

    a first access line driver coupled to the first memory access line; and

    a second access line driver coupled to the second memory access line,wherein the first and second access line drivers are configured to;

    provide a first voltage at a first polarity across the memory cell to write a first logic state to the memory cell,provide a second voltage at a second polarity across the memory cell to write a second logic state to the memory cell,provide a third voltage at the first polarity across the memory cell to write a third logic state to the memory cell, andprovide a fourth voltage at the second polarity across the memory cell to write a fourth logic state to the memory cell.

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