Configurable Gate Array Based on Three-Dimensional Writable Memory

• US 20180041216A1
• Filed: 10/13/2017
• Published: 02/08/2018
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,116,312 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable gate array based on three-dimensional writable memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function.

Claims

1. A configurable gate array, comprising:

at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and

at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.

2. The configurable gate array according to claim 1, wherein said first 3D-W array at least partially covers said configurable logic element.

3. The configurable gate array according to claim 1, further comprising at least a configurable interconnect.

4. The configurable gate array according to claim 1, wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.

5. The configurable gate array according to claim 1, further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function;

6. The configurable gate array according to claim 1, wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions.

7. A configurable gate array, comprising:

at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and

at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function.

8. The configurable gate array according to claim 7, wherein said first 3D-W array at least partially covers said configurable interconnect.

9. The configurable gate array according to claim 7, further comprising at least a configurable logic element.

10. The configurable gate array according to claim 7, wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.

11. The configurable gate array according to claim 7, further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function;

12. The configurable gate array according to claim 7, wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions.

13. A configurable gate array, comprising:

an array of configurable computing elements including a configurable computing element, wherein said configurable computing element is electrically programmable and can be loaded with a look-up table (LUT) for a math function;

an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;

an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects couple said array of configurable computing elements with said array of configurable logic elements;

wherein said configurable gate array realizes a math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects.

14. The configurable gate array according to claim 13, wherein at least a portion of said configurable computing element is formed in a three-dimensional writable memory (3D-W) array stacked above a semiconductor substrate.

15. The configurable gate array according to claim 14, wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.

16. The configurable gate array according to claim 14, wherein said 3D-W array at least partially covers said configurable logic element or said configurable interconnect.

17. The configurable gate array according to claim 14, wherein said 3D-W array is electrically re-programmable and said configurable computing element can be re-configured to realize different math functions.

18. The configurable gate array according to claim 13, wherein said configurable logic element is formed on said semiconductor substrate.

19. The configurable gate array according to claim 13, wherein said configurable interconnect is formed on said semiconductor substrate.

20. The configurable gate array according to claim 13, further comprising at least one multiplier.