ROBUST LINE CODING SCHEME FOR COMMUNICATION UNDER SEVERE EXTERNAL NOISES

• US 20180041304A1
• Filed: 10/13/2017
• Published: 02/08/2018
• Est. Priority Date: 05/09/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: SHEN, Ba-Zhong, CHINI, Ahmad, TU, Chung Ming, TAZEBAY, Mehmet Vakif
• Granted Patent: US 10,554,333 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

Abstract

A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Claims

1. A system comprising:

a media independent interface circuitry configured to receive, from an automobile component, binary data and corresponding management information to be transmitted via a communication link;

an encoder circuitry configured to generate forward error correction (FEC) frames that contain the binary data and the management information;

a scrambler circuitry configured to scramble the FEC frames comprising the binary data and the management information;

a data mapper circuitry configured to convert the scrambled FEC frames into pulse amplitude modulation (PAM) symbols; and

a communication interface circuitry configured to transmit the PAM symbols via the communication link.

2. The system of claim 1, wherein the data mapper circuitry is configured to convert the scrambled FEC frames into the PAM symbols according to a predetermined conversion scheme.

3. The system of claim 2, wherein the predetermined conversion scheme converts a predetermined amount of binary data from the scrambled FEC frames into a corresponding predetermined number of PAM symbols.

4. The system of claim 3, wherein conversion of the predetermined amount of binary data to the corresponding predetermined number of PAM symbols comprises mapping 3 binary bits into 8 pairs of voltage levels based on a 2D-PAM3 constellation.

5. The system of claim 1, wherein the scrambler circuitry is an additive scrambler, the additive scrambler configured to scramble bits of the binary data, bits of the management information, and bits of parity check frames generated by the encoder circuitry.

6. The system of claim 1, wherein the encoder circuitry determines a size of each FEC frame from the generated FEC frames, and the size is based on a predetermined transmission rate over the communication link.

7. The system of claim 1, further comprising:

a physical coding sublayer (PCS) framer circuitry configured to generate a PCS frame, the PCS frame comprising a predetermined number of bits of the binary data appended with a corresponding header information.

8. The system of claim 7, wherein the encoder circuitry is further configured to:

aggregate a first predetermined number of PCS frames from the PCS framer circuitry; and

generate a second predetermined number of FEC frames corresponding to the first predetermined number of PCS frames from the PCS framer.

9. The system of claim 8, wherein the encoder circuitry is further configured to generate parity check frames corresponding to the second predetermined number of FEC frames.

10. The system of claim 9, wherein the encoder circuitry is further configured to generate a management FEC frame comprising the management information.

11. A system comprising:

a physical media communication interface configured to receive ternary data from an automobile component over a physical media;

data de-mapper circuitry configured to convert the ternary data into binary data based on a predetermined mapping scheme;

de-scrambler circuitry configured to convert the binary data into a forward error correction (FEC) frame, the FEC frame comprising a plurality of symbols and parity check data;

decoder circuitry configured to decode, from the plurality of symbols, a plurality of data symbols and a management symbol; and

a media independent interface configured to transmit the plurality of data symbols and the management symbol to another automobile component for further processing.

12. The system of claim 11, wherein the ternary data is a two-dimensional pulse amplitude modulation (PAM3) symbol using a nine-point constellation.

13. The system of claim 11, wherein the physical media is a two conductor cable.

14. The system of claim 11, wherein the decoder is a Reed-Solomon decoder configured to generate data symbols of a predetermined size.

15. The system of claim 14, wherein the length of a data symbol is determined based on a predetermined transmission speed of the system.

16. The system of claim 11, wherein the de-scrambler circuitry comprises an additive de-scrambler.

17. The system of claim 11, wherein the data de-mapper circuitry is configured to aggregate a predetermined number of ternary data symbols prior to conversion of the aggregated ternary data symbols into the binary data based on the predetermined mapping scheme.

18. A method comprising:

receiving, via a media independent interface, media access control (MAC) layer data;

generating, by a physical coding sublayer (PCS) framer circuitry, PCS blocks corresponding to the MAC layer data;

aggregating, by an encoder circuitry, a predetermined number of PCS blocks;

appending, by the encoder circuitry, operations, administration, and maintenance (OAM) bits to the aggregated PCS blocks;

generating, by the encoder circuitry, forward error correction (FEC) frames comprising the aggregated PCS blocks and the OAM bits;

scrambling, by a data scrambler circuitry, the FEC frames comprising the aggregated PCS blocks and the OAM bits;

generating, by a data mapper, pulse amplitude modulation (PAM) symbols corresponding to the scrambled FEC frames; and

transmitting the PAM symbols via a communication link.

19. The method of claim 18, wherein the predetermined number of PCS blocks aggregated by the encoder is based on a target transmission rate.

20. The method of claim 19, wherein the predetermined number of PCS blocks aggregated by the encoder is further based on a predetermined length of each of the FEC frames.