MEMORY WITH KEEPER CIRCUIT

• US 20180047442A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/25/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HSU, Kuoyuan
• Granted Patent: US 10,090,042 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device with a keeper circuit is disclosed herein. The memory device (i) improves current tracking between the device'"'"'s memory cells and the keeper circuit, (ii) improves Vccmin for memory operations, and (iii) has an efficient circuit layout. The memory device includes a memory array with a plurality of bitlines coupled to the memory cells. The keeper circuit includes a plurality of switches and a current mirror circuit. The plurality of switches is respectively coupled to the plurality of bitlines. The current mirror circuit mirrors a bias current to a plurality of current mirror transistors respectively coupled to the plurality of switches.

Claims

1. A memory device, comprising:

a memory array comprising a plurality of bitlines coupled to a plurality of memory cells; and

a keeper circuit comprising;

a bias current generator configured to generate a bias current; and

a switch, coupled to a bitline of the plurality of bitlines, configured to;

couple the bitline to the bias current generator when the bitline is at a first logical level, and

decouple the bitline from the bias current generator when the bitline is at a second logical level.

2. The memory device of claim 1, wherein the bias current generator comprises:

a p-channel metal-oxide-semiconductor field-effect (PMOS) transistor; and

a diode-connected p-channel metal-oxide-semiconductor field-effect (PMOS) transistor,

wherein the PMOS transistor and the diode-connected PMOS transistor are configured and arranged to generate the bias current from a power supply voltage.

3. The memory device of claim 1, further comprising:

a current mirror transistor configured to mirror the bias current to provide a keeper current, wherein the switch is further configured to electrically connect the current mirror transistor to the bitline when the bitline is at the first logical level, and

wherein the switch is further configured to not electrically connect the current mirror transistor to the bitline when the bitline is at the second logical level.

4. The memory device of claim 3, wherein the keeper current is configured to charge the bitline to a voltage at or near a logic high voltage.

5. The memory device of claim 3, wherein the switch comprises:

an inverter having an input coupled to the bitline; and

a pass device, coupled to an output of the inverter, configured to;

pass the keeper current to the bitline when the bitline is at the first logical level, and

not pass the keeper current to the bitline when the bitline is at the second logical level.

6. The memory device of claim 5, wherein the pass device comprises:

a p-channel metal-oxide-semiconductor field-effect (PMOS) transistor.

7. The memory device of claim 3, wherein the bias current generator comprises:

a diode-connected p-channel metal-oxide-semiconductor field-effect (PMOS) transistor,

wherein a gate width of the current mirror transistor is sized equal to or smaller than a gate width of the diode-connected PMOS transistor.

8. The memory device of claim 1, wherein the keeper circuit further comprises:

a second switch, coupled to a second bitline of the plurality of bitlines, configured to;

couple the second bitline to the bias current generator when the second bitline is at the first logical level, and

decouple the second bitline from the bias current generator when the second bitline is at the second logical level.

9. The memory device of claim 8, further comprising:

a current mirror transistor configured to mirror the bias current to provide a keeper current,

wherein the switch is further configured to electrically connect the current mirror transistor to the bitline when the bitline is at the first logical level, and

wherein the switch is further configured to not electrically connect the current mirror transistor to the bitline when the bitline is at the second logical level; and

a second current mirror transistor configured to mirror the bias current to provide a second keeper current,

wherein the second switch is further configured to electrically connect the second current mirror transistor to the second bitline when the second bitline is at the first logical level, and

wherein the second switch is further configured to not electrically connect the second current mirror transistor to the second bitline when the second bitline is at the second logical level.

10. A memory device, comprising:

a memory array comprising a plurality of bitlines coupled to a plurality of memory cells; and

a keeper circuit comprising;

a switch coupled to a bitline of the plurality of bitlines;

means for generating a bias current;

means for mirroring the bias current to generate a keeper current; and

means for passing the keeper current to the switch,

wherein the switch is configured to;

couple the bitline to the means for passing when the bitline is at a first logical level; and

decouple the bitline from the means for passing when the bitline is at a second logical level.

11. The memory device of claim 10, wherein the keeper current is configured to charge the bitline to a voltage at or near a logic high voltage.

12. The memory device of claim 10, wherein the switch comprises:

an inverter having an input coupled to the bitline; and

a pass device, coupled to an output of the inverter, configured to;

pass the keeper current to the bitline when the bitline is at the first logical level, and

not pass the keeper current to the bitline when the bitline is at the second logical level.

13. The memory device of claim 12, wherein the pass device comprises:

a p-channel metal-oxide-semiconductor field-effect (PMOS) transistor.

14. The memory device of claim 10, wherein the keeper circuit further comprises:

a second switch, coupled to a second bitline of the plurality of bitlines, configured to;

couple the second bitline to the means for generating when the second bitline is at the first logical level, and

decouple the second bitline from the means for generating when the second bitline is at the second logical level.

15. The memory device of claim 14, wherein the keeper circuit further comprises:

second means for passing the keeper current to the second switch,

wherein the second switch is configured to;

couple the second bitline to the second means for passing when the second bitline is at the first logical level; and

decouple the second bitline from the second means for passing when the second bitline is at the second logical level.

16. A method, comprising:

generating a bias current;

mirroring the bias current to generate a keeper current;

passing the keeper current to a bitline of a plurality of bitlines when the bitline is at a first logical level; and

not passing the keeper current to the bitline when the bitline is at a second logical level.

17. The method of claim 16, wherein the passing comprises:

activating a switch to pass the keeper current to the bitline.

18. The method of claim 16, wherein the not passing comprises:

deactivating a switch to prevent the keeper current from being passed to the bitline.

19. The method of claim 16, further comprising:

mirroring the bias current to generate a second keeper current;

passing the second keeper current to a second bitline of the plurality of bitlines when the second bitline is at the first logical level; and

not passing the second keeper current to the second bitline when the second bitline is at the second logical level.

20. The method of claim 16, wherein the passing comprises:

passing the keeper current to generate a logic high voltage at the bitline.