Configurable Computing Array Comprising Three-Dimensional Writable Memory

• US 20180048313A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,075,168 B2
• Time in Patent Office: Days
• CPC Class Codes: B05B 11/0064 Lift valves B05B11/007 takes precedence
• CPC Class Codes: B05B 11/0072 A valve member forming part of an outlet opening
• CPC Class Codes: B05B 11/047 characterised by the outlet or venting means B05B11/041 and B05B11/042 take precedence
• CPC Class Codes: B05B 11/1022 actuated by pressure
• CPC Class Codes: B05B 11/1073 Springs
• CPC Class Codes: B05B 11/1097 with means for sucking back the liquid or other fluent material in the nozzle after a dispensing stroke
• CPC Class Codes: B65D 47/0838 located at an edge of the base element
• CPC Class Codes: B65D 47/2068 in which the stem is lowered by the pressure of the contents and thereby opening the valve
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit comprising an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which stores at least a portion of a look-up table (LUT) for a math function.

Claims

1. A configurable computing array, comprising:

at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and

at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array stores at least a first portion of a first look-up table (LUT) for a first math function;

wherein said configurable logic element and said configurable computing element are electrically coupled.

2. The configurable computing array according to claim 1, wherein said first 3D-W array at least partially covers said configurable logic element.

3. The configurable computing array according to claim 1, further comprising at least a configurable interconnect, wherein said configurable interconnect selectively couples said configurable logic element with said configurable computing element.

4. The configurable computing array according to claim 1, wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.

5. The configurable computing array according to claim 1, further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array stores at least a second portion of a second LUT for a second math function.

6. The configurable computing array according to claim 1, wherein said first 3D-W array is re-programmable and said first configurable computing element can be re-configured to realize different math functions.

7. A configurable computing array, comprising:

at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and

at least a configurable computing element, wherein said configurable computing element comprises a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, said first 3D-W array stores at least a first portion of a first look-up table (LUT) for a first math function;

wherein said configurable interconnect and said configurable computing element are electrically coupled.

8. The configurable computing array according to claim 7, wherein said first 3D-W array at least partially covers said configurable interconnect.

9. The configurable computing array according to claim 7, further comprising at least a configurable logic element, wherein said configurable logic element selectively couples said configurable interconnect with said configurable computing element

10. The configurable computing array according to claim 7, wherein said 3D-W array is a horizontal 3D-W array or a vertical 3D-W array.

11. The configurable computing array according to claim 7, further comprising at least a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array stores at least a second portion of a second LUT for a second math function.

12. The configurable computing array according to claim 7, wherein said first 3D-W array is re-programmable and said first configurable computing element can be re-configured to realize different math functions.

13. A configurable computing array, comprising:

an array of configurable computing elements including a configurable computing element, wherein said configurable computing element stores at least a portion of a look-up table (LUT) for a math function;

an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;

an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects selectively realizes an interconnect from an interconnect library;

wherein said configurable computing array realizes a math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects.

14. The configurable computing array according to claim 13, wherein said configurable logic element is formed on said semiconductor substrate.

15. The configurable computing array according to claim 13, wherein said configurable interconnect is formed on said semiconductor substrate.

16. The configurable computing array according to claim 13, wherein at least a portion of said configurable computing element is formed in a three-dimensional writable memory (3D-W) array stacked above a semiconductor substrate.

17. The configurable computing array according to claim 14, wherein said 3D-W array at least partially covers said configurable logic element.

18. The configurable computing array according to claim 14, wherein said 3D-W array at least partially covers said configurable interconnect.

19. The configurable computing array according to claim 14, wherein said 3D-W array is re-programmable and said configurable computing element can be re-configured to realize different math functions.

20. The configurable computing array according to claim 13, further comprising at least one multiplier.