Configurable Computing Array

• US 20180048314A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,084,453 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable computing array. It comprises an array of configurable computing elements and an array of configurable logic elements. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.

Claims

1. A configurable computing array, comprising:

an array of configurable computing elements including a configurable computing element, wherein said configurable computing element stores at least a portion of a look-up table (LUT) for a math function;

an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;

an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library;

wherein said configurable computing array realizes a math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects.

2. The configurable computing array according to claim 1, wherein said configurable computing element and said configurable logic element are both based on transistors and formed on a semiconductor substrate.

3. The configurable computing array according to claim 1, wherein said configurable interconnect selectively couples said configurable computing element and said configurable logic element.

4. The configurable computing array according to claim 1, wherein said configurable computing element comprises a writable-memory array.

5. The configurable computing array according to claim 4, wherein said writable-memory array is a RAM array.

6. The configurable computing array according to claim 4, wherein said writable-memory array is a ROM array.

7. The configurable computing array according to claim 6, wherein said ROM array is an OTP (one-time-programmable) array.

8. The configurable computing array according to claim 6, wherein said ROM array is an MTP (multiple-time-programmable) array.

9. The configurable computing array according to claim 8, wherein said configurable computing element can be re-configured to realize different math functions.

10. The configurable computing array according to claim 4 whose usage cycle includes a configuration stage, wherein the LUT for a math function is loaded into said writable-memory array.

11. The configurable computing array according to claim 4 whose usage cycle includes a computation stage, wherein a selected portion of the LUT for a math function is read out from said writable-memory array.

12. The configurable computing array according to claim 1, further comprising at least one multiplier.

13. A configurable computing array, comprising:

an array of configurable computing elements including a configurable computing element, wherein said configurable computing element stores at least a portion of a look-up table (LUT) for a math function;

an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library;

wherein said configurable computing array realizes a math function by programming said array of configurable computing elements and said array of configurable logic elements.

14. The configurable computing array according to claim 13, wherein said configurable computing element and said configurable logic element are both based on transistors and formed on a semiconductor substrate.

15. The configurable computing array according to claim 13, further comprising an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnects selectively couples said configurable computing element and said configurable logic element.

16. The configurable computing array according to claim 13, wherein said configurable computing element comprises a writable-memory array.

17. The configurable computing array according to claim 16, wherein said writable-memory array is re-programmable and said configurable computing element can be re-configured to realize different math functions.

18. The configurable computing array according to claim 16 whose usage cycle includes a configuration stage, wherein the LUT for a math function is loaded into said writable-memory array.

19. The configurable computing array according to claim 16 whose usage cycle includes a computation stage, wherein a selected portion of the LUT for a math function is read out from said writable-memory array.

20. The configurable computing array according to claim 13, further comprising at least one multiplier.