Configurable Computing Array Using Two-Sided Integration

• US 20180048316A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,141,939 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The present invention discloses a configurable computing array using two-sided integration. It is a monolithic integrated circuit comprising at least a configurable computing element located on one side of the substrate and at least a configurable logic element on the other side of the substrate. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.

Claims

1. A configurable computing array, comprising:

a semiconductor substrate having a first side and a second side;

at least a configurable computing element formed on said first side of said semiconductor substrate for storing at least a portion of a look-up table (LUT) for a math function;

at least a configurable logic element formed on said second side of said semiconductor substrate for selectively realizing a logic function from a logic library;

a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element;

wherein said configurable computing array realizes a math function by programming said configurable computing element and said configurable logic element.

2. The configurable computing array according to claim 1, wherein said first side is a front side;

and, said second side is a back side.

3. The configurable computing array according to claim 1, wherein said first side is a back side;

and, said second side is a front side.

4. The configurable computing array according to claim 1, wherein said through-substrate vias are through-silicon vias (TSV).

5. The configurable computing array according to claim 1, further comprising at least a configurable interconnect, wherein said configurable interconnect selectively couples said configurable computing element with said configurable logic element.

6. The configurable computing array according to claim 5, wherein said configurable interconnect is located on said first side.

7. The configurable computing array according to claim 5, wherein said configurable interconnect is located on said second side.

8. The configurable computing array according to claim 1, wherein said configurable computing element comprises a writable-memory array.

9. A configurable computing array, comprising:

a semiconductor substrate having a first side and a second side;

at least a configurable computing element formed on said first side of said semiconductor substrate for storing at least a portion of a look-up table (LUT) for a math function;

at least a configurable logic element formed on said second side of said semiconductor substrate for selectively realizing a logic function from a logic library;

a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing element and said configurable logic element;

at least a configurable interconnect for selectively realizing an interconnect from an interconnect library;

wherein said configurable computing array realizes a math function by programming said configurable computing element, said configurable logic element and said configurable interconnect.

10. The configurable computing array according to claim 9, wherein said first side is a front side;

and, said second side is a back side.

11. The configurable computing array according to claim 9, wherein said first side is a back side;

and, said second side is a front side.

12. The configurable computing array according to claim 9, wherein said through-substrate vias are through-silicon vias (TSV).

13. The configurable computing array according to claim 9, wherein said configurable interconnect selectively couples said configurable computing element and said configurable logic element.

14. The configurable computing array according to claim 9, wherein said configurable interconnect is located on said first side.

15. The configurable computing array according to claim 9, wherein said configurable interconnect is located on said second side.

16. The configurable computing array according to claim 9, wherein said configurable computing element comprises a writable-memory array.

17. The configurable computing array according to claim 16, wherein said writable-memory array is re-programmable and said configurable computing element can be re-configured to realize different math functions.

18. The configurable computing array according to claim 16 whose usage cycle includes a configuration stage, wherein the LUT for a math function is loaded into said writable-memory array.

19. The configurable computing array according to claim 16 whose usage cycle includes a computation stage, wherein a selected portion of the LUT for a math function is read out from said writable-memory array.

20. The configurable computing array according to claim 9, further comprising at least one multiplier.