Configurable Computing-Array Package

• US 20180048317A1
• Filed: 10/25/2017
• Published: 02/15/2018
• Est. Priority Date: 03/05/2016
• Status: Abandoned Application

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Application Number:
  US15/793,968
• Publication Number:
  US 20180048317A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses a configurable computing-array package. It comprises a configurable computing die including an array of configurable computing elements and a configurable logic die including an array of configurable logic elements. Each configurable computing element comprises at least a writable-memory array, which stores at least a portion of a look-up table (LUT) for a math function.

Claims

1. A configurable computing-array package, comprising:

a configurable computing die comprising at least a configurable computing element for storing at least a portion of a look-up table (LUT) for a math function;

a configurable logic die comprising at least a configurable logic element for selectively realizing a logic function from a logic library;

a plurality of inter-die connections for coupling said configurable computing die and said configurable logic die;

wherein said configurable computing-array package realizes a math function by programming said configurable computing element and said configurable logic element.

2. The configurable computing-array package according to claim 1, further comprising at least a configurable interconnect for selectively coupling said configurable computing element and said configurable logic element.

3. The configurable computing-array package according to claim 2, wherein said configurable interconnect is located on said configurable computing die.

4. The configurable computing-array package according to claim 2, wherein said configurable interconnect is located on said configurable logic die.

5. The configurable computing-array package according to claim 1, wherein said configurable computing element comprises a writable-memory array.

6. The configurable computing-array package according to claim 1, wherein said inter-die connections are micro-bumps.

7. The configurable computing-array package according to claim 1, wherein said inter-die connections are through-silicon-vias (TSV).

8. The configurable computing-array package according to claim 1, further comprising at least one multiplier.

9. The configurable computing-array package according to claim 1, wherein said configurable computing die and said configurable logic die are vertically stacked.

10. A configurable computing-array package, comprising:

a configurable computing die comprising at least a configurable computing element for storing at least a portion of a look-up table (LUT) for a math function;

a configurable logic die comprising at least a configurable logic element for selectively realizing a logic function from a logic library;

at least a configurable interconnect for selectively realizing an interconnect from an interconnect library;

a plurality of inter-die connections for coupling said configurable computing die and said configurable logic die;

wherein said configurable computing-array package realizes a math function by programming said configurable computing element, said configurable logic element and said configurable interconnect.

11. The configurable computing-array package according to claim 10, wherein said configurable interconnect selectively couples said configurable computing element and said configurable logic element.

12. The configurable computing-array package according to claim 10, wherein said configurable interconnect is located on said configurable computing die.

13. The configurable computing-array package according to claim 10, wherein said configurable interconnect is located on said configurable logic die.

14. The configurable computing-array package according to claim 10, wherein said configurable computing element comprises a writable-memory array.

15. The configurable computing-array package according to claim 14, wherein said writable-memory array is a RAM array or a ROM array.

16. The configurable computing-array package according to claim 14 wherein said writable-memory array is re-programmable and said configurable computing element can be re-configured to realize different math functions.

17. The configurable computing-array package according to claim 10, wherein said inter-die connections are micro-bumps.

18. The configurable computing-array package according to claim 10, wherein said inter-die connections are through-silicon-vias (TSV).

19. The configurable computing-array package according to claim 10, further comprising at least one multiplier.

20. The configurable computing-array package according to claim 10, wherein said configurable computing die and said configurable logic die are vertically stacked.