METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS
First Claim
1. An analog-to-digital conversion (ADC) block comprising:
- an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal;
a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and
a differential analog-to-digital converter (ADC) comprising a voltage-controlled oscillator (VCO), two counters, and an error generator block,wherein the VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals, wherein each of the two counters receives a respective pulse signal from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two digital counters and generates a digital conversion code corresponding to a difference between the digital counter values.
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Accused Products
Abstract
An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.
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Citations
22 Claims
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1. An analog-to-digital conversion (ADC) block comprising:
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an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) comprising a voltage-controlled oscillator (VCO), two counters, and an error generator block, wherein the VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals, wherein each of the two counters receives a respective pulse signal from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two digital counters and generates a digital conversion code corresponding to a difference between the digital counter values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving two analog input signals, a primary-precision configuration signal, and a fractional-precision configuration signal; generating a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; generating a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and converting the second pair of differential signals to a digital conversion code corresponding to a difference between the two analog input signals using a differential analog-to-digital converter (ADC), wherein the differential ADC comprises a voltage-controlled oscillator (VCO), two counters, and an error generator block, and wherein the VCO included in the ADC receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals, wherein each of the two counters receives a respective pulse signal of the two pulse signals from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two counters and generates a digital conversion code corresponding to a difference between the two digital counter values. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification