METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS

• US 20180048324A1
• Filed: 08/09/2017
• Published: 02/15/2018
• Est. Priority Date: 08/09/2016
• Status: Active Grant

• Current Assignee: Andapt Holdings Limited
• Original Assignee: AnDAPT, Inc.
• Inventors: Samad, Maheen, Crotty, Patrick J., Birkner, John, Cheung, Herman, Shankar, Kapil
• Granted Patent: US 9,998,135 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/1014 at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

Claims

1. An analog-to-digital conversion (ADC) block comprising:

an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal;

a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and

a differential analog-to-digital converter (ADC) comprising a voltage-controlled oscillator (VCO), two counters, and an error generator block,

wherein the VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals, wherein each of the two counters receives a respective pulse signal from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two digital counters and generates a digital conversion code corresponding to a difference between the digital counter values.

2. The ADC block of claim 1, wherein the primary-precision configuration signal and the plurality of fractional-precision configuration signals are received from a programmable fabric of a programmable logic device (PLD).

3. The ADC block of claim 1, wherein the differential ADC further comprises a first ADC including a first VCO and a second ADC including a second VCO, and the first VCO and the second VCO have different precision settings for converting the two analog input signals based on the primary-precision configuration signal and a plurality of fractional-precision configuration signals.

4. The ADC block of claim 1, wherein the amplifier block comprises one or more resistors and one or more multiplexers corresponding to the one or more resistors, each of the one or more multiplexers is configured to programmably adjust a ratio of a corresponding resistor by connecting to a tapping point among a predetermined set of tapping points based on the primary-precision configuration signal, and each tapping point of the predetermined set of tapping points provides a different ratio of the corresponding resistor.

5. The ADC block of claim 4, wherein the amplifier block further comprises an amplifier that generates the first pair of differential signals based on ratios of the one or more resistors.

6. The ADC block of claim 1, wherein the configuration block comprises two resistors and four multiplexers, and each of the four multiplexer is configured to programmably adjust a ratio of a corresponding resistor by connecting to a tapping point among a predetermined set of tapping points based on the fractional-precision configuration signal, and each tapping point of the predetermined set of tapping points provides a different ratio of the corresponding resistor.

7. The ADC block of claim 1, wherein the VCO included in the differential ADC comprises:

a voltage-to-current converter and two current-controlled oscillators (ICOs).

8. The ADC block of claim 7, wherein the two ICOs are arranged from a substantially equal distance from ICO mirror circuits and receive current inputs from the ICO mirror circuits through transistor legs, wherein the two ICOs are separated from each other by a separation area, and wherein the transistor legs feeding the current inputs from the ICO mirror circuits are positioned in the separation area.

9. The ADC block of claim 1, wherein the differential ADC further comprises:

two clock latch blocks and two counter latch blocks.

10. The ADC block of claim 1, further comprising a calibration switch and a calibration register, wherein the calibration switch is closed in response to a calibration signal to provide two reference analog signals to the ADC block, and the error generator block is configured to store an offset digital conversion code corresponding to the two reference analog signals in the calibration register.

11. The ADC block of claim 10, wherein the error generator block is configured to subtract the offset digital conversion code to generate a calibrated digital conversion code corresponding to the two analog input signals.

12. A method comprising:

receiving two analog input signals, a primary-precision configuration signal, and a fractional-precision configuration signal;

generating a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal;

generating a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and

converting the second pair of differential signals to a digital conversion code corresponding to a difference between the two analog input signals using a differential analog-to-digital converter (ADC),

wherein the differential ADC comprises a voltage-controlled oscillator (VCO), two counters, and an error generator block, and

wherein the VCO included in the ADC receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals, wherein each of the two counters receives a respective pulse signal of the two pulse signals from the VCO and generates a digital counter value, and wherein the error generator block receives digital counter values from the two counters and generates a digital conversion code corresponding to a difference between the two digital counter values.

13. The method of claim 12, wherein the primary-precision configuration signal and the plurality of fractional-precision configuration signals are received from a programmable fabric of a programmable logic device (PLD).

14. The method of claim 12, wherein the differential ADC further comprises a first ADC including a first VCO and a second ADC including a second VCO, and the method further comprising:

setting different precision setting for the first VCO and the second VCO based on the primary-precision configuration signal and a plurality of fractional-precision configuration signals.

15. The method of claim 12, further comprising:

programmably adjusting a ratio of a resistor by connecting to a tapping point among a predetermined set of tapping points based on the primary-precision configuration signal, wherein each tapping point of the predetermined set of tapping points provides a different ratio of the corresponding resistor.

16. The method of claim 12, wherein the VCO further comprises:

a voltage-to-current converter, two current-controlled oscillators (ICOs), and the differential ADC further comprises two clock latch blocks connected between the two ICOs and the two counters, the method further comprising;

latching the two clock latch blocks at an expiry of a sampling period and halting clocks of the two ICOs after a first delay from the latching of the two clock latch blocks.

17. The method of claim 16, wherein the differential ADC further comprises two counter latch blocks between the two counters and the error generator block, the method further comprising:

generating a pulse signal to the two counter latch blocks to capture the digital counter values after a second delay from the first delay.

18. The method of claim 16, further comprising:

receiving a programable count value;

comparing the digital counter values against the programmable count value; and

generating a latching signal to latch the two clock latch blocks when one of the digital counter values reaches the programmable count value indicating the expiry of the sampling period.

19. The method of claim 16, further comprising:

receiving a programable time value; and

generating a latching signal to latch the two clock latch blocks when the sampling period reaches over the programmable time value indicating the expiry of the sampling period.

20. The method of claim 12, further comprising:

generating a ready signal indicating that the digital counter values are ready to be read by the error generator block.

21. The method of claim 12, further comprising closing a calibration switch in response to a calibration signal to provide two reference analog signals to the ADC block, storing an offset digital conversion code corresponding to the two reference analog signals in a calibration register.

22. The method of claim 21, further comprising:

subtracting the offset digital conversion code to generate a calibrated digital conversion code corresponding to the two analog input signals.