Semiconductor Packages and Methods of Forming the Same

• US 20180053730A1
• Filed: 01/17/2017
• Published: 02/22/2018
• Est. Priority Date: 08/19/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shao, Tung-Liang, Tung, Chih-Hang, Yu, Chen-Hua
• Granted Patent: US 9,997,467 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/11424 Immersion coating, e.g. in a solder bath immersion processes C23C2/00
• CPC Class Codes: H01L 2224/1144 by transfer printing
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13616 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/22 : of a plurality of HDI interconnects
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32147 : the layer connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/32237 : the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/80143 : Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80905 : Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81143 : Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.

Claims

1. A method comprising:

forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess, wherein the first recess has a slanted sidewall that extends continuously from the opening of the first recess to the bottom of the first recess;

forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device;

placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, wherein after the first device is placed into the first recess, the bottom end of the first device is spaced apart from the bottom of the first recess; and

bonding a sidewall of the first device to a sidewall of the first recess.

2. The method of claim 1, wherein the slanted sidewall of the first recess having a substantially constant sidewall angle with respect to a top surface of the first substrate, wherein the sidewall angle of the first recess is not substantially perpendicular to the top surface of the first substrate.

3. The method of claim 2, wherein the sidewall of the first device has a substantially constant angle with respect to a top surface of the first device that is about the same as the sidewall angle of the first recess.

4. The method of claim 2, wherein the sidewall angle is about 54.7 degrees.

5. The method of claim 1, further comprising forming a redistribution layer over the first device and over the first substrate.

6. The method of claim 1, further comprising forming a second recess in the first substrate and further comprising placing a second device in the second recess.

7. The method of claim 6, wherein the first device comprises a first semiconductor material and the second device comprises a second semiconductor material that is different than the first semiconductor material.

8. The method of claim 1, wherein placing a first device into the first recess comprises sliding a portion of a sidewall of the first device along a portion of the slanted sidewall of the first recess, the sidewall of the first device physically contacting the slanted sidewall of the first recess.

9. The method of claim 1, wherein forming the first device comprises removing portions of a dielectric layer disposed on a second substrate.

10. A method comprising:

attaching a first semiconductor device and a second semiconductor device to a supporting film; and

aligning the first semiconductor device to a substrate, the aligning comprising;

inserting a protruding portion of the first semiconductor device at least partially into a first recess formed in a top surface of the substrate, wherein the protruding portion of the first semiconductor device has a tapered profile, and wherein the inserting causes a translation of the first semiconductor device both laterally and toward a bottom surface of the substrate, wherein the second semiconductor device is attached to the supporting film and disposed further from the substrate than the first semiconductor device while the first semiconductor device is being aligned to the substrate.

11. The method of claim 10, further comprising impinging a sidewall of the protruding portion of the first semiconductor device on a sidewall of the first recess.

12. The method of claim 10, further comprising leveling a top surface of the first semiconductor device with respect to the top surface of the substrate.

13. The method of claim 10, further comprising bonding the first semiconductor device to the substrate.

14. The method of claim 13, wherein the bonding comprises forming a direct bond between the first semiconductor device and the substrate.

15. The method of claim 10, wherein a height of the protruding portion of the first semiconductor device is less than a depth of the first recess.

16. The method of claim 10, wherein the protruding portion of the first semiconductor device comprises a dielectric material.

17. The method of claim 10, further comprising detaching the first semiconductor device from the supporting film.

18. A semiconductor device comprising:

a substrate comprising a plurality of recesses in a top surface of the substrate, wherein a depth of the plurality of recesses is smaller than a thickness of the substrate, wherein the depth and the thickness are measured along a direction from the top surface of the substrate to a bottom surface of the substrate opposing the top surface; and

a plurality of chiplets disposed respectively in the plurality of recesses, wherein the plurality of chiplets are bonded to the substrate, wherein a bottom of at least one of the plurality of chiplets is separate from a bottom of at least one of the plurality of recesses.

19. The semiconductor device of claim 18, wherein a first chiplet of the plurality of chiplets comprises a different semiconductor material than a second chiplet of the plurality of chiplets.

20. The semiconductor device of claim i8, further comprising a redistribution layer disposed over the plurality of chiplets and the substrate, wherein the redistribution layer is electrically connected to the plurality of chiplets.