ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE
First Claim
1. An array substrate, comprising:
- a substrate, gate lines and data lines arranged on the substrate crossing each other, a plurality of pixel zones arranged in an array and defined by the gate lines and the data lines, and a pixel switch, a storage capacitor, and at least one control capacitor in each of the plurality of pixel zones, wherein;
the pixel switch comprises at least two transistors connected in series, wherein gates of the at least two transistors are connected with one of the gate lines, a first transistor among the at least two transistors connected in series is connected with one terminal of the storage capacitor, and a last transistor among the at least two transistors connected in series is connected with one of the data lines; and
the number of the at least one control capacitor is less than the number of the at least two transistors;
the control capacitor comprises a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent ones of the transistors; and
the control capacitor is configured to control the potential of the second electrode of the control capacitor to be kept at the potential of a data signal loaded on the data line, when an active gate scan signal is stopped from being loaded on the gate line.
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Accused Products
Abstract
The invention discloses an array substrate, a display panel, and a display device, where at least one control capacitor is added to a pixel zone, and the control capacitor has a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent transistors, so that when an active gate scan signal is stopped from being loaded on a gate line, the potential of the second electrode of the control capacitor is controlled to be kept at the potential of data signal loaded on a data line, to thereby lower the difference in voltage between the source and the drain of a transistor associated with the second electrode of the control capacitor so as to keep the potential at a connection point of the transistor with a storage capacitor to be the potential of a data signal loaded on the data line.
13 Citations
20 Claims
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1. An array substrate, comprising:
a substrate, gate lines and data lines arranged on the substrate crossing each other, a plurality of pixel zones arranged in an array and defined by the gate lines and the data lines, and a pixel switch, a storage capacitor, and at least one control capacitor in each of the plurality of pixel zones, wherein; the pixel switch comprises at least two transistors connected in series, wherein gates of the at least two transistors are connected with one of the gate lines, a first transistor among the at least two transistors connected in series is connected with one terminal of the storage capacitor, and a last transistor among the at least two transistors connected in series is connected with one of the data lines; and the number of the at least one control capacitor is less than the number of the at least two transistors;
the control capacitor comprises a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent ones of the transistors; and
the control capacitor is configured to control the potential of the second electrode of the control capacitor to be kept at the potential of a data signal loaded on the data line, when an active gate scan signal is stopped from being loaded on the gate line.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A display panel comprising:
an array substrate, the array substrate comprises; a substrate, gate lines and data lines arranged on the substrate crossing each other, a plurality of pixel zones arranged in an array and defined by the gate lines and the data lines, and a pixel switch, a storage capacitor, and at least one control capacitor in each of the plurality of pixel zones, wherein; the pixel switch comprises at least two transistors connected in series, wherein gates of the at least two transistors are connected with one of the gate lines, a first transistor among the at least two transistors connected in series is connected with one terminal of the storage capacitor, and a last transistor among the at least two transistors connected in series is connected with one of the data lines; and the number of the at least one control capacitor is less than the number of the at least two transistors;
the control capacitor comprises a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent ones of the transistors; and
the control capacitor is configured to control the potential of the second electrode of the control capacitor to be kept at the potential of a data signal loaded on the data line, when an active gate scan signal is stopped from being loaded on the gate line.
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20. A display device, comprising:
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a display panel including; an array substrate, the array substrate having; a substrate, gate lines and data lines arranged on the substrate crossing each other, a plurality of pixel zones arranged in an array and defined by the gate lines and the data lines, and a pixel switch, a storage capacitor, and at least one control capacitor in each of the plurality of pixel zones, wherein; the pixel switch comprises at least two transistors connected in series, wherein gates of the at least two transistors are connected with one of the gate lines, a first transistor among the at least two transistors connected in series is connected with one terminal of the storage capacitor, and a last transistor among the at least two transistors connected in series is connected with one of the data lines; and the number of the at least one control capacitor is less than the number of the at least two transistors;
the control capacitor comprises a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent ones of the transistors; and
the control capacitor is configured to control the potential of the second electrode of the control capacitor to be kept at the potential of a data signal loaded on the data line, when an active gate scan signal is stopped from being loaded on the gate line.
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Specification