FABRICATION OF VERTICAL FIN TRANSISTOR WITH MULTIPLE THRESHOLD VOLTAGES

• US 20180053848A1
• Filed: 10/13/2017
• Published: 02/22/2018
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Karthik, Cheng, Kangguo, Hashemi, Pouya, Reznicek, Alexander
• Granted Patent: US 10,991,823 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0825 Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
• CPC Class Codes: H01L 27/0828 Combination of direct and inverse vertical transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10K 2101/80 Composition varying spatially, e.g. having a spatial gradient

Abstract

A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Claims

1. A method of fabricating a pair of vertical fin field effect transistors, comprising:

epitaxially growing a first vertical fin of silicon-germanium on a substrate;

epitaxially growing a second vertical fin of silicon-germanium on the substrate;

forming a cap on the top surface of the first vertical fin;

forming a protective cap over the top surface and sidewalls of the second vertical fin before oxidizing the sidewalls of the first vertical fin, so only the sidewalls of the first vertical fin form silicon oxide layers;

oxidizing the sidewalls of the first vertical fin to form silicon oxide layers at least on opposite sides of the first vertical fin, and increasing the germanium concentration of the first vertical fin; and

removing the silicon oxide layers to form a portion of the first vertical fin having a reduced width.

2. The method of claim 1, wherein the substrate is crystalline silicon.

3. The method of claim 1, further comprising,

removing the protective cap from the second vertical fin and the cap from the top surface of the first vertical fin.

4. The method of claim 3, further comprising, forming a bottom spacer on the substrate;

forming a gate structure on the first vertical fin; and

forming a gate structure on the second vertical fin.

5. The method of claim 4, further comprising forming shallow trench isolation in the substrate, wherein the shallow trench isolation is between the location of the first vertical fin and the location of the second vertical fin.

6. The method of claim 1, wherein the concentration of germanium in at least a portion of the first vertical fin is greater than the concentration of germanium in the second vertical fin.

7. The method of claim 6, wherein at least a portion of the first vertical fin has a vertically graded germanium concentration.

8. The method of claim 6, wherein the first vertical fin with the reduced width has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

9. The method of claim 8, wherein the first vertical fin with the reduced width has a greater germanium concentration than the second vertical fin.

10. The method of claim 9, wherein the first vertical fin with the reduced width has a reduced threshold voltage compared to the second vertical fin.

11. A method of fabricating a pair of vertical fin field effect transistors, comprising:

epitaxially growing a first vertical fin of silicon-germanium on a single-crystal silicon substrate;

epitaxially growing a second vertical fin of silicon-germanium on the single-crystal silicon substrate;

forming a cap on the top surface of the first vertical fin;

forming a protective cap over the top surface and sidewalls of the second vertical fin before oxidizing the sidewalls of the first vertical fin, so only the sidewalls of the first vertical fin form silicon oxide layers;

oxidizing the sidewalls of the first vertical fin to form silicon oxide layers at least on opposite sides of the first vertical fin, and increasing the germanium concentration of the first vertical fin;

removing the silicon oxide layers to form a portion of the first vertical fin having a reduced width; and

removing the protective cap from the second vertical fin and the cap from the top surface of the first vertical fin.

12. The method of claim 11, further comprising, forming a gate structure on the first vertical fin, and forming a gate structure on the second vertical fin.

13. The method of claim 12, wherein the gate structure on the first vertical fin and the gate structure on the second vertical fin each includes a gate dielectric layer and a gate conductor layer.

14. The method of claim 13, further comprising, forming a first source/drain region on the first vertical fin, and forming a second source/drain region on the second vertical fin.

15. The method of claim 14, further comprising, forming a shallow trench isolation region between the first vertical fin and second vertical fin.

16. A method of fabricating a pair of vertical fin field effect transistors, comprising:

forming a shallow trench isolation region in a single-crystal silicon substrate;

forming a hardmask layer on the single-crystal silicon substrate and the shallow trench isolation region;

forming a first trench on one side of the shallow trench isolation region, and a second trench on the opposite side of the shallow trench isolation region from the first trench;

forming a silicon-germanium fin material in the first trench and the second trench;

forming a capped portion over the first trench;

oxidizing the silicon-germanium fin material to form a silicon oxide layer, a graded fin material over the second trench, and a modified vertical fin having an upper portion with an increased germanium concentration in the second trench;

removing the capped portion and silicon oxide layer; and

removing the silicon-germanium fin material and graded fin material.

17. The method of claim 16, further comprising, removing the hardmask layer to expose an unmodified vertical fin and the modified vertical fin.

18. The method of claim 17, further comprising, forming a gate structure on the modified vertical fin, and a gate structure on the unmodified vertical fin.

19. The method of claim 18, wherein the modified vertical fin has a second portion with a vertically graded germanium concentration.

20. The method of claim 19, further comprising, forming a first source/drain region on the top of the unmodified vertical fin, and a second source/drain region on the top of the modified vertical fin.