FLIPPED BITS FOR ERROR DETECTION AND CORRECTION FOR SYMBOL TRANSITION CLOCKING TRANSCODING
First Claim
1. A method of transmitting data on a multi-wire interface, comprising:
- providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to be transmitted;
providing an error detection constant (EDC) as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted;
converting the word to he transmitted into a transition number; and
transmitting the transition number as a sequence of symbols on the multi-wire interface,wherein the transition number is expressed using a numeral system based on a maximum number of possible states per symbol, andwherein a length of the EDC is at least one bit and the EDC may have a known, fixed value and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.
1 Assignment
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Accused Products
Abstract
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One such method includes providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to hit-order of the word to be transmitted, providing an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted, converting the word to be transmitted into a transition number, and transmitting the transition number as a sequence of symbols on the multi-wire interface. The EDC may have a length and a known, fixed value, and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.
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Citations
28 Claims
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1. A method of transmitting data on a multi-wire interface, comprising:
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providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to be transmitted; providing an error detection constant (EDC) as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted; converting the word to he transmitted into a transition number; and transmitting the transition number as a sequence of symbols on the multi-wire interface, wherein the transition number is expressed using a numeral system based on a maximum number of possible states per symbol, and wherein a length of the EDC is at least one bit and the EDC may have a known, fixed value and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a communications transceiver coupled to a multi-wire interface, and configured to provide a plurality of data bits in a word to he transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to he transmitted; an error constant insertion circuit configured to append an error detection constant (EDC) to the plurality of data bits in the word to be transmitted, wherein the EDC comprises one or more least significant bits of the word to he transmitted and positioned adjacent to a most significant bit of the plurality of data bits in the word to be transmitted; an encoder configured to convert the word to be transmitted into a transition number; and a transmitter circuit configured to transmit the transition number as a sequence of symbols on the multi-wire interface, wherein a length of the EDC is at least one bit and a known, fixed value selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method of receiving data from a multi-wire interface, comprising:
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receiving a sequence of symbols from a plurality of connectors; converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors; converting the transition number into a plurality of bits; and determining whether a symbol error has occurred during transmission of the sequence of symbols based on a value of an error detection constant (EDC) included in the plurality of bits, wherein the EDC has a known, fixed value and a length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. An apparatus comprising:
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a clock recovery circuit configured to extract a clock signal from a sequence of symbols transmitted from a plurality of connectors, wherein the clock signal is used to receive the sequence of symbols; means for converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors; means for converting the transition number into a plurality of bits; and means for determining whether a symbol error has occurred during transmission of the sequence of symbols based on a value of an error detection constant (EDC) included in the plurality of bits, wherein the EDC has a known, fixed value and a length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors.
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Specification