FLIPPED BITS FOR ERROR DETECTION AND CORRECTION FOR SYMBOL TRANSITION CLOCKING TRANSCODING

• US 20180054216A1
• Filed: 08/10/2017
• Published: 02/22/2018
• Est. Priority Date: 08/22/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: SENGOKU, Shoichiro
• Application Number:
  US15/673,678
• Publication Number:
  US 20180054216A1
• Time in Patent Office: Days
• CPC Class Codes: H03M 13/095 Error detection codes other than CRC and single parity bit codes
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One such method includes providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to hit-order of the word to be transmitted, providing an EDC as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted, converting the word to be transmitted into a transition number, and transmitting the transition number as a sequence of symbols on the multi-wire interface. The EDC may have a length and a known, fixed value, and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.

Claims

1. A method of transmitting data on a multi-wire interface, comprising:

providing a plurality of data bits in a word to be transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to be transmitted;

providing an error detection constant (EDC) as one or more least significant bits of the word to be transmitted and adjacent to a most significant bit of the plurality of data bits in the word to be transmitted;

converting the word to he transmitted into a transition number; and

transmitting the transition number as a sequence of symbols on the multi-wire interface,

wherein the transition number is expressed using a numeral system based on a maximum number of possible states per symbol, and

wherein a length of the EDC is at least one bit and the EDC may have a known, fixed value and length selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.

2. The method of claim 1, further comprising:

generating each symbol in the sequence of symbols using a digit of the transition number and a preceding symbol in the sequence of symbols, wherein clock information is embedded in transitions between consecutive symbols in the sequence of symbols.

3. The method of claim 1, wherein the length and the known, fixed value of the EDC are selected such that a transmission error affecting the one or more symbols in the sequence of symbols results in the EDC having a value different from the known, fixed value when decoded.

4. The method of claim 1, wherein the EDC is provided as a number of bits, the number being determined based on a number of symbols in the sequence of symbols and a total number of states per symbol available for encoding data transmissions on the multi-wire interface.

5. The method of claim 1 wherein the EDC includes 8 bits.

6. The method of claim 1, further comprising:

providing control bits in the word to be transmitted in more significant bits than bits assigned to carry the plurality of data bits.

7. The method of claim 1, further comprising:

selecting a level of error detection or correction for a transaction on the multi-wire interface;

configuring the length of the EDC in accordance with the level of error detection or correction selected; and

defining a number of bits in the plurality of data bits in accordance with the length of the EDC.

8. A device comprising:

a communications transceiver coupled to a multi-wire interface, and configured to provide a plurality of data bits in a word to he transmitted such that a bit-order of the plurality of data bits is flipped with respect to bit-order of the word to he transmitted;

an error constant insertion circuit configured to append an error detection constant (EDC) to the plurality of data bits in the word to be transmitted, wherein the EDC comprises one or more least significant bits of the word to he transmitted and positioned adjacent to a most significant bit of the plurality of data bits in the word to be transmitted;

an encoder configured to convert the word to be transmitted into a transition number; and

a transmitter circuit configured to transmit the transition number as a sequence of symbols on the multi-wire interface,

wherein a length of the EDC is at least one bit and a known, fixed value selected to enable a decoder to detect or correct one or more symbol errors in the sequence of symbols.

9. The device of claim 8, wherein the encoder is configured to generate each symbol in the sequence of symbols using a digit of the transition number and a preceding symbol, and wherein dock information is embedded in transitions between consecutive symbols in the sequence of symbols.

10. The device of claim 8, wherein the length and the known, fixed value of the EDC are selected such that a transmission error affecting the one or more symbols in the sequence of symbols results in the EDC having a value different from the known, fixed value when decoded.

11. The device of claim 8, wherein the error constant insertion circuit is configured to:

provide the EDC in a number of bits, the number being determined based on a number of symbols in the sequence of symbols.

12. The device of claim 8, wherein the error constant insertion circuit is configured to:

provide the EDC in a number of bits, the number being determined based on a total number of states per symbol available for encoding data transmissions on the multi-wire interface.

13. The device of claim 8, wherein the EDC includes 8 bits.

14. The device of claim 8, wherein the communications transceiver is configured to:

provide control bits in the word to he transmitted in more significant bits than bits assigned to carry the plurality of data bits.

15. The device of claim 8, further comprising a processor configured to:

select a level of error detection or correction for a transaction on the multi-wire interface;

configure a length of the EDC in accordance with the level of error detection or correction selected; and

define a number of bits in the plurality of data bits in accordance with the length of the EDC.

16. A method of receiving data from a multi-wire interface, comprising:

receiving a sequence of symbols from a plurality of connectors;

converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors;

converting the transition number into a plurality of bits; and

determining whether a symbol error has occurred during transmission of the sequence of symbols based on a value of an error detection constant (EDC) included in the plurality of bits,

wherein the EDC has a known, fixed value and a length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors.

17. The method of claim 16, further comprising:

determining that a symbol error has occurred when multiple symbol errors are present in the sequence of symbols,

wherein the known, fixed value and the length of the EDC are selected to enable detection of transmission errors affecting a plurality of symbols in the sequence of symbols.

18. The method of claim 16, wherein the transition number is expressed using a numeral system based on a maximum number of possible symbol transitions between a pair of consecutive symbols transmitted on the plurality of connectors.

19. The method of claim 16, wherein the one or two symbol errors cause a decoded version of the EDC to have a value that is different from the known, fixed value.

20. The method of claim 16, wherein the EDC is provided as a number of least significant bits in the plurality of bits, the number of least significant bits being determined based on a total number of states per symbol available for encoding data transmissions on the plurality of connectors.

21. The method of claim 20, wherein the number of least significant bits is determined based on a total number of symbols used to encode the plurality of bits.

22. The method of claim 20, wherein the plurality of connectors comprises a number (N) single-ended connectors, the total number of states per symbol available for encoding data transmissions is 2^N−

x, wherein x is at least 1.

23. The method of claim 20, wherein the plurality of connectors comprises a number (N) of connectors that conduct multi-level differential signals, the total number of states per symbol available for encoding data transmissions is N!−

x, wherein x is at least 1.

24. The method of claim 16, wherein the total number of states available at each transition is 3 and the EDC includes 8 bits.

25. The method of claim 16, wherein the total number of states available at each transition is 3, the sequence of symbols includes 17 or more symbols, and the EDC includes 9 bits.

26. The method of claim 16, wherein the total number of states available at each transition is 5 and the EDC includes 10 bits.

27. The method of claim 16, wherein the total number of states available at each transition is 5, the sequence of symbols includes 8 or more symbols, and the EDC includes 11 bits.

28. An apparatus comprising:

a clock recovery circuit configured to extract a clock signal from a sequence of symbols transmitted from a plurality of connectors, wherein the clock signal is used to receive the sequence of symbols;

means for converting the sequence of symbols into a transition number, each digit of the transition number representing a transition between two consecutive symbols transmitted on the plurality of connectors;

means for converting the transition number into a plurality of bits; and

means for determining whether a symbol error has occurred during transmission of the sequence of symbols based on a value of an error detection constant (EDC) included in the plurality of bits,

wherein the EDC has a known, fixed value and a length determined based on a total number of states per symbol defined for encoding data transmissions on the plurality of connectors.