Clock and Data Recovery Having Shared Clock Generator
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Abstract
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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Citations
21 Claims
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1. (canceled)
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2. An apparatus, comprising:
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receivers, each to receive a respective data signal arriving via a respective signaling lane, each data signal transmitted in response to a common clock source and carrying a respective embedded clock, wherein each of the receivers is to generate a respective local error signal representing timing error between the respective embedded clock and timing derived from a global clock; a controllable oscillator to generate an oscillation signal in response to a first control signal; and a delay locked loop to receive the oscillation signal and to generate an output, the global clock dependent on the output, the delay locked loop to impart delay in response to a second control signal; wherein the first control signal and the second control signal are each to be generated as a function of the local error signals generated by the receivers. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit (IC), comprising:
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receivers, each to receive a respective data signal arriving via a respective signaling lane, each data signal being generated externally from said integrated circuit, being transmitted in response to a common clock source and carrying a respective embedded clock, wherein each of the receivers is to generate a respective local error signal representing timing error between the respective embedded clock and timing derived from a global clock; a controllable oscillator to generate an oscillation signal in response to a first control signal; and a delay locked loop to receive the oscillation signal and to generate an output, the global clock dependent on the output, the delay locked loop to impart delay in response to a second control signal; wherein the first control signal and the second control signal are each to be generated as a function of the local error signals generated by the receivers. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method, comprising:
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via receivers, receiving respective data signals arriving via respective signaling lanes, each data signal transmitted in response to a common clock source and carrying a respective embedded clock, and generating respective local error signals representing timing error between the respective embedded clocks and timing derived from a global clock; controlling an oscillator to generate an oscillation signal in response to a first control signal; and using a delay locked loop to receive the oscillation signal, to impart delay in response to a second control signal, and to generate an output; wherein the global clock is dependent on the output; and wherein the method further comprises generating the first control signal and the second control signal, each as a function of the local error signals generated by the receivers. - View Dependent Claims (20, 21)
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Specification