MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20180059937A1
• Filed: 03/17/2017
• Published: 03/01/2018
• Est. Priority Date: 08/25/2016
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Jee-Yul
• Application Number:
  US15/461,606
• Publication Number:
  US 20180059937A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/74 : using duplex memories, i.e. using dual copies

Abstract

A memory system comprises a memory device including a normal cell region and a redundancy cell region, and a controller suitable for programming data in duplicate in both the normal and the redundancy cell regions, wherein when detecting an error in the data read from the normal cell region, the controller invalidates the data of the normal cell region and validates the data of the redundancy cell region.

Claims

1. A memory system comprising:

a memory device including a normal cell region and a redundancy cell region; and

a controller suitable for programming data in duplicate in both the normal and the redundancy cell regions,

wherein when detecting an error in the data read from the normal cell region, the controller invalidates the data of the normal cell region and validates the data of the redundancy cell region.

2. The memory system of claim 1, wherein the controller comprises:

an address generation unit suitable for generating first and second physical addresses of the respective normal and redundancy cell regions corresponding to a logical address of the data; and

an address mapping unit suitable for mapping the logical address to the first and second physical addresses, and validates or invalidates the data of the normal and redundancy cell regions by validating or invalidating the first and second addresses depending on detection of an error in the data read from the normal cell region.

3. The memory system of claim 2, wherein the controller further comprises an error detection and correction unit suitable for detecting and correcting the error in the data.

4. The memory system of claim 3, wherein, when detecting an error in the data read from the normal cell region, the address mapping unit invalidates the first address and validates the second address.

5. The memory system of claim 4, wherein the controller further copies data corresponding to the validated second address of the redundancy cell region into the normal cell region.

6. The memory system of claim 5, wherein the address mapping unit further maps the logical address of the data to a physical address of the copied data in the normal cell region with the second address and validates the physical address of the copied data as the first address of the data, and invalidates the second address.

7. The memory system of claim 2, wherein, during a garbage collection operation to the normal cell region, when a region corresponding to the first address is selected as a victim region, the address mapping unit further invalidates the first address and validates the second address.

8. The memory system of claim 2, wherein the controller disables the second physical address generated by the address generation unit when a free space of the memory device is less than a reference value.

9. The memory system of claim 1,

wherein the normal cell region includes a plurality of multi-level cell memory blocks, and

wherein the redundancy cell region includes a plurality of single-level cell memory blocks.

10. The memory system of claim 1, wherein the normal and redundancy cell regions respectively includes first and second memory chips sharing a channel and operative by a single chip enable signal.

11. The memory system of claim 10, wherein said duplicate programming is performed through a single transmission operation of the data from the controller to both the normal cell region and the redundancy cell region.

12. The memory device of claim 1, wherein the memory device is a flash memory.

13. An operating method for a memory system, the operating method comprising:

programming data in duplicate both into a normal cell region and a redundancy cell region of a memory device of the memory system;

detecting an error in the data read from the normal cell region;

invalidating the data programmed in the normal cell region; and

validating the data programmed in the redundancy cell region.

14. The operating method of claim 13,

wherein the programming of the data comprises:

generating first and second physical addresses of the respective normal and redundancy cell regions corresponding to a logical address of the data;

mapping the logical address to the first and second physical addresses; and

validating the first address and invalidating the second address.

15. The operating method of claim 14, wherein the invalidating and validating of the data of the normal and redundancy cell regions is performed by validating or invalidating the first and second addresses depending on detection of an error in the data read from the normal cell region.

16. The operating method of claim 15, further comprising copying data corresponding to the validated second address of the redundancy cell region into the normal cell region.

17. The operating method of claim 16, further comprising:

mapping the logical address of the data to a physical address of the copied data in the normal cell region with the second address;

validating the physical address of the copied data as the first address of the data; and

invalidating the second address.

18. The operating method of claim 14, further comprising performing a garbage collection operation to the normal cell region.

19. The operating method of claim 18, further comprising, when a region corresponding to the first address is selected as a victim region:

invalidating the first address; and

validating the second address.

20. The operating method of claim 13, wherein the memory device is a flash memory.