DATA ERROR DETECTION IN COMPUTING SYSTEMS

• US 20180060168A1
• Filed: 08/25/2016
• Published: 03/01/2018
• Est. Priority Date: 08/25/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Kelly, Bryan, Bulusu, Mallik, Nguyen, Tom
• Granted Patent: US 10,025,649 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Claims

1. A method for ensuring data integrity in a computing device having a processor, a memory, a memory controller, and a persistent storage interconnected to one another, the method comprising:

receiving, at the memory controller, a data request from the persistent storage to copy data from the memory;

in response to the received data request, retrieving the requested data from the memory, the retrieved data containing data bits and corresponding error correcting bits;

determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits; and

in response to determining that the retrieved data bits contain one or more data integrity errors, writing data representing existence of the one or more data integrity errors into a memory location or register accessible by the processor, the data written into the memory location being retrievable by the processor to generate a log file in the persistent storage indicating the existence of the one or more integrity errors.

2. The method of claim 1 wherein the error correcting bits are configured to store dual-error detecting, single-error correcting codes for the corresponding data bits.

3. The method of claim 1 wherein the error checking data is retrievable by the processor to generate the log file in the persistent storage indicating the existence of the one or more integrity errors when an operating system of the computing device is suspended in the computing device.

4. The method of claim 1 wherein the error correcting bits are structured to provide dual-error detection, the error correcting code values indicating an existence of two flipped bits in the corresponding protected data bits, and wherein determining whether the retrieved data bits contain one or more data integrity errors includes determining whether the data bits contain two flipped bits based on the error correcting code.

5. The method of claim 1 wherein:

the processor includes a processor cache;

the memory location accessible by the processor includes a set of model-specific registers in the processor cache; and

writing the data into the memory location includes writing the data into the set of model-specific registers in the processor cache.

6. The method of claim 1 further comprising in response to determining that the retrieved data bits do not contain one or more data integrity errors, writing additional data representing a lack of data integrity errors into the memory location accessible by the processor.

7. A computing device having a processor with a machine check register, a memory, a memory controller, and a persistent storage interconnected to one another, the memory containing instructions executable by the processor to cause the processor to perform a process comprising:

accessing, with the processor, the machine check register for data indicating an existence of or a lack of one or more data integrity errors in data copied from the memory to the persistent storage by the memory controller;

determining whether the accessed data indicates that the data being copied include one or more data integrity errors based on the accessed data in the machine check register; and

in response to determining that the accessed data indicates that the data being copied include one or more data integrity errors, generating and storing a log file in the persistent storage indicating the existence of one or more integrity errors associated with the data copied to the persistent storage from the memory.

8. The computing device of claim 7 wherein:

a copy of the data in the memory contains both data bits and corresponding error correcting bits;

another copy of the data in the persistent storage containing only the data bits without the error correcting bits; and

generating and storing the log file include generating and storing the log file in the persistent storage indicating the existence of one or more integrity errors associated with the data bits of the data copied to the persistent storage from the memory.

9. The computing device of claim 7 wherein:

determining whether the accessed data indicates that the data being copied include one or more data integrity errors includes determining whether the accessed data indicates that the data being copied include one or more two flipped bits; and

generating and storing the log file includes generating and storing the log file in the persistent storage indicating the existence of two flipped bits in the data copied to the persistent storage from the memory.

10. The computing device of claim 7 wherein generating and storing the log file includes updating an entry in the log file in the persistent storage, the entry indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

11. The computing device of claim 7 wherein generating and storing the log file includes creating the log file in the persistent storage, the created log file including data indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

12. The computing device of claim 7 wherein accessing the machine check register includes executing instructions while an operating system of the computing device is suspended.

13. The computing device of claim 7 wherein accessing the machine check register includes executing instructions to access the machine check register periodically while an operating system of the computing device is suspended, the executed instructions being a part of a software package independent of the operating system of the computing device.

14. The computing device of claim 7 wherein the machine check register includes a set of model-specific registers in a processor cache of the processor, and wherein accessing the machine check register includes accessing the set of model-specific registers for the data indicating the existence of or the lack of one or more data integrity errors in the data copied from the memory to the persistent storage by the memory controller.

15. The computing device of claim 7 wherein the process performed by the processor further includes detecting a power failure of a main power supply associated with the processor or a request for a system shutdown and in response, transmitting a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from a portion of the main memory designated as a software implemented non-volatile dual in-line memory module using power from an auxiliary power source.

16. The computing device of claim 7 wherein the process performed by the processor further includes:

detecting a power failure of a main power supply associated with the processor or a request for a system shutdown;

in response to the detected power failure of the main power supply or the request for a system shutdown, transmitting a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from a portion of the main memory designated as a software implemented non-volatile dual in-line memory module using power from an auxiliary power source;

receiving an indication from the persistent storage that data persistence is completed; and

in response to receiving the indication, allowing the computing device to shut down.

17. A computing device having a processor, a memory, and a persistent storage interconnected to one another via a data bus, the memory containing instructions executable by the processor to cause the processor to perform a process comprising:

restoring data from the persistent storage to the memory for processing, the restored data including multiple data bits without any error correcting bit;

accessing a log file from the persistent storage, the log file being stored separately from the restored data in the persistent storage and containing other data indicating whether the restored data contains one or more data integrity errors;

determining whether the restored data contains one or more data integrity errors based on the other data in the retrieved log file; and

in response to determining that the restored data contains one or more data integrity errors, indicating to an operating system of the computing device that the restored data is invalid.

18. The computing device of claim 17 wherein restoring the data from the persistent storage to the memory for processing includes restoring the data from the persistent storage to a portion of the memory designated as a software implemented non-volatile dual in-line memory module.

19. The computing device of claim 17 wherein the process performed by the processor further includes in response to determining that the restored data does not contain one or more data integrity errors, indicating to an operating system of the computing device that the restored data is valid and ready for further processing.

20. The computing device of claim 17 wherein the restoring, accessing, and determining operations are performed during a system reset in the computing device.