FERROELECTRIC MEMORY CELLS

• US 20180061468A1
• Filed: 08/16/2017
• Published: 03/01/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derner, Scott J., Kawamura, Christopher J.
• Granted Patent: US 10,153,018 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2253 Address circuits or decoders
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

Claims

1. An apparatus, comprising:

a first capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to a plate line structure;

a second capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to the plate line structure;

a first transistor vertically displaced relative to the first capacitor and coupled to the second plate of the first capacitor; and

a second transistor vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor.

2. The apparatus of claim 1 wherein the first transistor includes a first semiconductor pillar extending from the second plate of the first capacitor and the second transistor includes a second semiconductor pillar extending from the second plate of the second capacitor.

3. The apparatus of claim 2 wherein the first transistor includes a channel region within the first semiconductor pillar and source/drain regions included in the first semiconductor pillar.

4. The apparatus of claim 1 wherein the first transistor includes a first semiconductor pillar disposed between the second plate of the first capacitor and a digit line.

5. The apparatus of claim 1 wherein the first transistor and the second transistor are vertically displaced relative to one another.

6. The apparatus of claim 1 wherein the first plates of the first and second capacitor share a common composition with the plate line structure.

7. The apparatus of claim 1 wherein the first transistor and the second transistor are laterally displaced relative to one another.

8. The apparatus of claim 1 wherein the first and second transistors are in a common horizontal plane and the first and second transistors include respective gates along a word line that extends along the horizontal plane.

9. The apparatus of claim 1 wherein the first transistor and the first capacitor are included in a first memory cell and the second transistor and the second capacitor are included in a second memory cell, and wherein the first and second capacitors are vertically displaced relative to one another and wherein the plate line structure is shared by the first and second memory cells.

10. An apparatus, comprising:

a first memory cell; and

a second memory cell;

wherein each memory cell comprises;

a first transistor;

a first ferroelectric capacitor including a ferroelectric material, coupled to the first transistor and vertically displaced relative to the first transistor;

a second transistor; and

a second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor.

11. The apparatus of claim 10, further comprising:

a plate line structure shared by the first and second memory cells.

12. The apparatus of claim 11 wherein the first and second memory cells are laterally displaced relative to one another.

13. The apparatus of claim 10 wherein the first and second memory cells are vertically displaced on opposing sides of one of a plate line structure shared by the first and second memory cells or a digit line shared by the first and second memory cells.

14. The apparatus of claim 10, further comprising:

a first digit line shared by the first and second memory cells; and

a second digit line shared by the first and second memory cells.

15. The apparatus of claim 10, further comprising:

a first digit line shared by the first and second memory cells;

a second digit line coupled to the first memory cell; and

a third digit line coupled to the second memory cell.

16. An apparatus, comprising:

a first ferroelectric capacitor including first and second plates;

a second ferroelectric capacitor including first and second plates, wherein the first and second ferroelectric capacitors are vertically displaced relative to one another;

a first transistor including a first semiconductor pillar coupled to the second plate of the first ferroelectric capacitor and disposed between the first capacitor and a first digit line; and

a second transistor including a second semiconductor pillar coupled to the second plate of the second ferroelectric capacitor and disposed between the second capacitor and a second digit line.

17. The apparatus of claim 16 wherein the first and second digit lines are in a common horizontal plane.

18. The apparatus of claim 16, further comprising:

a third transistor including a third semiconductor pillar coupled to the first plates of the first and second capacitors and disposed between the first and second capacitors and a plate line structure.

19. The apparatus of claim 18 wherein the third semiconductor pillar has a different dimension for of at least one of a channel length or a channel width.

20. The apparatus of claim 18 wherein the third transistor is vertically displaced relative to the first and second transistors.

21. The apparatus of claim 20 wherein the third transistor is above the first and second transistors.

22. The apparatus of claim 20 wherein the third transistor is below the first and second transistors.

23. The apparatus of claim 16, further comprising:

a third transistor including a third semiconductor pillar coupled to the first plate of the first capacitor and disposed between the first capacitor and a plate line structure; and

a fourth transistor including a fourth semiconductor pillar coupled to the first plate of the second capacitor and disposed between the second capacitor and the plate line structure.

24. An apparatus, comprising:

a first capacitor including first and second plates, and further including a ferroelectric material disposed between the first and second plates;

a second capacitor including first and second plates, and further including a ferroelectric material disposed between the first and second plates;

a first vertical transistor disposed between the second plate of the first capacitor and a first digit line;

a second vertical transistor disposed between the second plate of the second capacitor and a second digit line; and

a third vertical transistor disposed between the first plates of the first and second capacitors and a plate line structure, wherein the third vertical transistor is vertically displaced from the first and second vertical transistors.

25. The apparatus of claim 24 wherein the first and second transistors are in a common horizontal plane.

26. The apparatus of claim 24, further comprising:

a first word line including gates of the first and second transistors; and

a second word line including a gate of the third transistor.

27. The apparatus of claim 26 wherein the first word line extends along a first horizontal plane and the second word line extends along a second horizontal plane that is vertically displaced from the horizontal plane of the first word line.

28. The apparatus of claim 24 wherein first and second capacitors, and the first, second, and third vertical transistors are included in a first memory cell, and wherein the first and second digit lines are shared with a second memory cell over which the first memory cell is stacked.

29. The apparatus of claim 24 wherein first and second capacitors, and the first, second, and third vertical transistors are included in a first memory cell, and wherein the plate line structure is shared with a second memory cell over which the first memory cell is stacked.

30. An apparatus, comprising:

a first ferroelectric capacitor including first and second plates;

a second ferroelectric capacitor including first and second plates;

a first vertical transistor disposed between the second plate of the first ferroelectric capacitor and a first digit line;

a second vertical transistor disposed between the first plate of the first ferroelectric capacitor and a plate line structure, wherein the first vertical transistor is vertically displaced from the second vertical transistor;

a third vertical transistor disposed between the second plate of the second ferroelectric capacitor and a second digit line; and

a fourth vertical transistor disposed between the first plate of the second ferroelectric capacitor and the plate line structure, wherein the third vertical transistor is vertically displaced from the fourth vertical transistor.

31. The apparatus of claim 30 wherein the first, second, third, and fourth vertical transistors are in a common vertical plane.

32. The apparatus of claim 30 wherein first and third vertical transistors are in a first common horizontal plane as one another and the second and fourth vertical transistors are in a second common horizontal plane as one another.

33. The apparatus of claim 32 wherein the first common horizontal plane is vertically displaced from the second common horizontal plane.

34. The apparatus of claim 32, further comprising a word line including gates of the first and third transistors, wherein the word line extends along the first common horizontal plane.

35. The apparatus of claim 30 wherein first and second ferroelectric capacitors, and the first, second, third, and fourth vertical transistors are included in a first memory cell, and wherein the first and second digit lines are shared with a second memory cell over which the first memory cell is stacked.

36. The apparatus of claim 30 wherein first and second ferroelectric capacitors, and the first, second, third, and fourth vertical transistors are included in a first memory cell, and wherein the plate line structure is shared with a second memory cell over which the first memory cell is stacked.

37. The apparatus of claim 30 wherein each of the first, second, third, and fourth transistors comprises:

a semiconductor pillar;

a gate dielectric material;

a channel region in the semiconductor pillar; and

source/drain regions in the semiconductor pillar.

38. A method of accessing a memory cell, comprising:

activating first and second transistors of the memory cell;

applying a voltage to a plate line coupled to first and second ferroelectric capacitors, the first ferroelectric capacitor coupled to the first transistor and vertically displaced relative to the first transistor and the second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor; and

comparing a first voltage developed at a first digit line coupled to the first ferroelectric capacitor to a second voltage developed at a second digit line coupled to the second ferroelectric capacitor.