Non-Volatile Memory Devices Having Temperature and Location Dependent Word Line Operating Voltages

• US 20180061504A1
• Filed: 03/17/2017
• Published: 03/01/2018
• Est. Priority Date: 08/26/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jisuk, Park, IL Han, Park, Se Hwan
• Granted Patent: US 10,176,881 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A non-volatile memory device includes: a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells; a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells; a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and control a to compensation for the read voltage based on a read temperature offset.

Claims

1. A non-volatile memory device, comprising:

a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells;

a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells;

a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and

a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and then control a compensation for the read voltage based on a read temperature offset,

wherein the compensation for the program verification voltage and the compensation for the read voltage are performed in correspondence with each other in order to eliminate a deviation due to a difference between the read temperature offset and the program verification temperature offset,

wherein the plurality of word lines is divided into a plurality of word line groups including two or more word lines, and

the control circuit sets a program verification temperature offset and a read temperature offset in a corresponding word line group among the plurality of word line groups according to a distance between one word line in each of the plurality of word line groups and the ground selection line and an operation temperature.

2. The non-volatile memory device of claim 1, wherein:

an absolute value of the program verification temperature offset or the read temperature offset is sequentially increased when the distance between one word line in each of the plurality of word line groups and the ground selection line is increased.

3. The non-volatile memory device of claim 2, wherein:

the program verification temperature offset corresponds to the read temperature offset.

4. The non-volatile memory device of claim 2, wherein:

the program verification temperature offset or the read temperature offset is further increased in a negative direction when the operation temperature is decreased.

5. The non-volatile memory device of claim 1, wherein:

the control circuit controls the compensation for the read voltage based on a back pattern compensation offset, and

a size of the back pattern compensation offset is sequentially decreased when the distance between one word line in each of the plurality of word line groups and the ground selection line is increased.

6. The non-volatile memory device of claim 1, wherein:

the control circuit controls the compensation for the program verification voltage based on a back pattern compensation offset, and

a size of the back pattern compensation offset is sequentially decreased when the distance between one word line in each of the plurality of word line groups and the ground selection line is increased.

7. The non-volatile memory device of claim 1, wherein:

the memory cell array includes single level cells and multi-level cells, and

the program verification temperature offset or the read temperature offset corresponding to the single level cells is different from the program verification temperature offset or the read temperature offset corresponding to the multi-level cells.

8. A non-volatile memory device having a 3D structure, comprising:

a plurality of memory cell strings formed by laminating a plurality of memory cells in a vertical direction to a substrate;

a plurality of word lines connected to a ground selection transistor of each of the plurality of memory cell strings, and a plurality of serially connected non-volatile memory cells;

a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and

a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and then control a compensation for the read voltage based on a read temperature offset,

wherein the compensation for the program verification voltage and the compensation for the read voltage are performed in correspondence with each other in order to eliminate a deviation due to a difference between the read temperature offset and the program verification temperature offset,

wherein the plurality of word lines is divided into a plurality of word line groups including two or more word lines, and

the control circuit sets a program verification temperature offset and a read temperature offset in a corresponding word line group among the plurality of word line groups according to a distance between one word line in each of the plurality of word line groups and the substrate and an operation temperature.

9. The non-volatile memory device of claim 8, wherein:

an absolute value of the program verification temperature offset or the read temperature offset is sequentially increased when the distance between one word line in each of the plurality of word line groups and the substrate is increased.

10. The non-volatile memory device of claim 9, wherein:

the program verification temperature offset corresponds to the read temperature offset.

11. The non-volatile memory device of claim 9, wherein:

the program verification temperature offset or the read temperature offset is further increased in a negative direction when the operation temperature is decreased.

12. The non-volatile memory device of claim 8, wherein:

the control circuit compensates for and increases the read voltage when a distance between the plurality of word line and the substrate is increased.

13. The non-volatile memory device of claim 8, wherein:

the control circuit compensates for and increases the program verification voltage when a distance between the plurality of word line and the substrate is increased.

14. A non-volatile memory device, comprising:

a memory cell array including a plurality of word lines including first and second word lines;

a voltage generator configured to generate a program verification voltage to be applied to the plurality of word lines during a program verification and a read voltage to be applied to the plurality of word lines during a data read; and

a control circuit configured to generate a verification offset for compensating for the verification voltage based on a temperature during the program verification and a position of a word line, to which the verification voltage is to applied, and then generate a read offset for compensating for the read voltage based on a temperature during the data read and the position of a word line, to which the read voltage is to be applied, and control a change direction between the verification offset and the read offset,

wherein the compensation for the program verification voltage and the compensation for the read voltage are performed in correspondence with each other in order to eliminate a deviation due to a difference between the read temperature offset and the program verification temperature offset,

wherein the plurality of word lines is divided into a plurality of word line groups including word lines having the number based on an operation temperature,

the control circuit sets a verification offset and a read offset in a corresponding word line group among the plurality of word line groups according to a position of one word line in each of the plurality of word line groups and an operation temperature, and

each of the first word line and the second word line belongs to a different word line group.

15. The non-volatile memory device of claim 14, wherein:

the control circuit sets a first verification offset for compensating for a program verification voltage to be applied to the first word line to be higher than a second verification offset for compensating for a verification voltage to be applied to the second word line, and sets a first read offset for compensating for a read voltage to be applied to the first word line to be higher than a second read offset for compensating for a read voltage to be applied to the second word line.

16. The non-volatile memory device of claim 14, wherein:

the first and second verification offsets and the first and second read offsets are changed according to a temperature.

17. The non-volatile memory device of claim 16, wherein:

the control circuit sets the first verification offset when a temperature during the program verification is a first temperature to be lower than the first verification offset when a temperature during the program verification is a second temperature higher than the first temperature, and sets the first read offset when a temperature during the data read is the first temperature to be lower than the first read offset when a temperature during the data read is the second temperature.

18. The non-volatile memory device of claim 17, wherein:

the memory cell array includes a plurality of memory cells connected to a bit line and the plurality of word line, and

a memory cell connected to the second word line among the plurality of memory cells is more closely connected to the bit line than the memory cell connected to the first word line.

19. The non-volatile memory device of claim 17, wherein:

the memory cell array includes a plurality of memory cells connected to a bit line and the plurality of word line, and

a memory cell connected to the first word line among the plurality of memory cells is more closely connected to the bit line than the memory cell connected to the second word line.

20. The non-volatile memory device of claim 14, wherein:

the control circuit changes the verification offset and the read offset in the same direction in proportion to a position of the plurality of word lines.