VERTICAL FUSE STRUCTURES

• US 20180061759A1
• Filed: 10/30/2017
• Published: 03/01/2018
• Est. Priority Date: 08/25/2016
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Juntao, Wang, Junli, Yang, Chih-Chao
• Granted Patent: US 10,032,717 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Claims

1. A semiconductor device, comprising:

a plurality of vertical semiconductor fins formed on a semiconductor substrate, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;

a vertical fuse device comprising a metallic fuse element formed over a portion of the first vertical semiconductor fin, wherein the metallic fuse element comprises a first conformal metallic layer formed on the portion of the first vertical semiconductor fin, and a first metallic electrode layer formed on the first conformal metallic layer; and

a FINFET (Fin Field Effect Transistor) device comprising a metallic gate electrode formed over a portion of the second vertical semiconductor fin, wherein the metallic gate electrode comprises a high-k metallic gate stack structure conformally formed on the portion of the second vertical semiconductor fin and a second metallic electrode layer formed on the high-k metallic gate stack structure, wherein the high-k metallic gate stack structure comprises a conformal layer of dielectric material formed on the portion of the second vertical semiconductor fin and a second conformal metallic layer formed on the conformal layer of dielectric material;

wherein the first conformal metallic layer and the second conformal metallic layer are patterned from a same conformal layer of metallic material; and

wherein the first metallic electrode layer and the second metallic electrode layer are patterned from a same layer of metallic material.

2. The device of claim 1, wherein the metallic fuse element of the vertical fuse device and the metallic gate electrode of the FINFET device are concurrently formed as part of a RMG (replacement metal gate) process.

3. The device of claim 1, further comprising:

a first fuse contact formed in contact with the metallic fuse element of the vertical fuse device; and

a second fuse contact formed in contact with a portion of the first vertical semiconductor fin adjacent to the vertical fuse device.

4. The device of claim 1, wherein the metallic fuse element is formed between insulating sidewall spacers of the vertical fuse device, and wherein the metallic gate electrode is formed between insulating sidewall spacers of the FINFET device.

5. The device of claim 1, wherein the conformal layer of metallic material that is patterned to form the first conformal metallic layer and the second conformal metallic layer comprises a work function metallic material that is utilized to obtain a target work function for the high-k metallic gate stack structure of the metallic gate electrode of the FINFET device.

6. The device of claim 1, wherein the conformal layer of metallic material that is patterned to form the first conformal metallic layer and the second conformal metallic layer comprises at least one of TaN, TiN, and TiAlC.

7. The device of claim 1, wherein the conformal layer of dielectric material comprises a high-k dielectric material having a dielectric constant k of about 3.0 or greater.

8. The device of claim 1, wherein the layer of metallic material that is patterned to form the first metallic electrode layer and the second metallic electrode layer comprises at least one of Al, W, Co and a metal silicide.

9. The device of claim 1, further comprising a first capping layer formed on the metallic fuse element of the vertical fuse device and a second capping layer formed on the metallic gate electrode of the FINFET device.

10. The device of claim 9, further comprising:

a first vertical contact formed through the first capping layer in contact with the metallic fuse element of the vertical fuse device; and

a second vertical contact formed through the second capping layer in contact with the metallic gate electrode of the FINFET device.

11. A semiconductor device, comprising:

a plurality of vertical semiconductor fins formed on a semiconductor substrate, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;

a vertical fuse device comprising;

a metallic fuse element formed over a portion of the first vertical semiconductor fin, wherein the metallic fuse element comprises a first conformal metallic layer formed on the portion of the first vertical semiconductor fin, and a first metallic electrode layer formed on the first conformal metallic layer;

a first insulating sidewall spacer surrounding the metallic fuse element; and

a first capping layer formed on an upper surface of the metallic fuse element; and

a FINFET (Fin Field Effect Transistor) device comprising;

a metallic gate electrode formed over a portion of the second vertical semiconductor fin, wherein the metallic gate electrode comprises a high-k metallic gate stack structure conformally formed on the portion of the second vertical semiconductor fin and a second metallic electrode layer formed on the high-k metallic gate stack structure, wherein the high-k metallic gate stack structure comprises a conformal layer of dielectric material formed on the portion of the second vertical semiconductor fin and a second conformal metallic layer formed on the conformal layer of dielectric material;

a second insulating sidewall spacer surrounding the metallic gate electrode; and

a second capping layer formed on an upper surface of the metallic fuse element;

wherein the first conformal metallic layer and the second conformal metallic layer are patterned from a same conformal layer of metallic material; and

wherein the first metallic electrode layer and the second metallic electrode layer are patterned from a same layer of metallic material.

12. The device of claim 11, wherein the metallic fuse element of the vertical fuse device and the metallic gate electrode of the FINFET device are concurrently formed as part of a RMG (replacement metal gate) process.

13. The device of claim 11, further comprising:

a first fuse contact formed in contact with the metallic fuse element of the vertical fuse device; and

a second fuse contact formed in contact with a portion of the first vertical semiconductor fin adjacent to the vertical fuse device.

14. The device of claim 11, wherein the conformal layer of metallic material that is patterned to form the first conformal metallic layer and the second conformal metallic layer comprises a work function metallic material that is utilized to obtain a target work function for the high-k metallic gate stack structure of the metallic gate electrode of the FINFET device.

15. The device of claim 11, wherein the conformal layer of metallic material that is patterned to form the first conformal metallic layer and the second conformal metallic layer comprises at least one of TaN, TiN, and TiAlC.

16. The device of claim 11, wherein the conformal layer of dielectric material comprises a high-k dielectric material having a dielectric constant k of about 3.0 or greater.

17. The device of claim 11, wherein the layer of metallic material that is patterned to form the first metallic electrode layer and the second metallic electrode layer comprises at least one of Al, W, Co and a metal silicide.

18. The device of claim 11, further comprising:

a first vertical contact formed through the first capping layer in contact with the metallic fuse element of the vertical fuse device; and

a second vertical contact formed through the second capping layer in contact with the metallic gate electrode of the FINFET device.

19. The device of claim 11, further comprising:

a second metallic fuse element formed over a second portion of the first vertical semiconductor fin, wherein second the metallic fuse element comprises;

a third conformal metallic layer formed on the portion of the first vertical semiconductor fin, and a third metallic electrode layer formed on the second conformal metallic layer;

a third insulating sidewall spacer surrounding the second metallic fuse element; and

a third capping layer formed on an upper surface of the second metallic fuse element.

20. The device of claim 19, further comprising a fuse contact formed in contact with a portion of the first vertical semiconductor fin disposed between the first and second metallic fuse elements.