LOW PROFILE PASSIVE ON GLASS (PoG) DEVICE COMPRISING A DIE

• US 20180061775A1
• Filed: 08/31/2016
• Published: 03/01/2018
• Est. Priority Date: 08/31/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Velez, Mario, Mudakatte, Niranjan Sunil, Yun, Changhan, Berdy, David, Gu, Shiqun, Kim, Jonghae, Zuo, Chengjie
• Application Number:
  US15/253,782
• Publication Number:
  US 20180061775A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19102 : in a stacked assembly with the semiconductor or solid state device
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

Claims

1. A device comprising:

a single substrate layer comprising;

a first surface;

a second surface being substantially opposite to the first surface; and

a cavity that passes through the second surface of the single substrate;

a plurality of interconnects over the first surface of the single substrate layer, the plurality of interconnects configured to operate as at least one passive component;

a substrate interconnect coupled to the plurality of interconnects, wherein the substrate interconnect is formed (i) partially in the cavity of the single substrate layer such that the cavity is partially unfilled, and (ii) over the second surface of the single substrate layer such that the substrate interconnect travels at least laterally along the second surface of the single substrate;

a first die coupled to the single substrate layer and the plurality of interconnects; and

an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component.

2. The device of claim 1, wherein the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μ

m) or less.

3. The device of claim 1, wherein the single substrate layer comprises a thickness of about 50-75 microns (μ

m).

4. The device of claim 1, wherein the encapsulation layer comprises a thickness of about 100 microns (μ

m) or less.

5. The device of claim 1, wherein the single substrate layer comprises a single layer of glass or a single layer of silicon.

6. The device of claim 1, wherein a portion of the cavity that substantially passes through the single substrate layer.

7. The device of claim 1, wherein the at least one passive component comprises an inductor.

8. The device of claim 1, further comprising a second die coupled to the single substrate layer and the plurality of interconnects.

9. The device of claim 8, wherein the plurality of interconnects is configured to operate as a first inductor and a second inductor, the first inductor coupled to the first die, and the second inductor coupled to the second die,

10. The device of claim 1, wherein the device is incorporated into a. device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an, automotive vehicle.

11. An apparatus comprising:

a single substrate layer;

a means for passive functionality located over the single substrate layer;

a first die coupled to the single substrate layer and the means for passive functionality, the first die comprising a plurality of solder interconnects that is directly coupled to the means for passive functionality; and

an encapsulation layer that at least partially encapsulates the first die and the means for passive functionality.

12. The apparatus of claim 11, wherein the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μ

m) or less.

13. The apparatus of claim 11, wherein the single substrate layer comprises a thickness of about 50-75 microns (μ

m).

14. The apparatus of claim 11, wherein the encapsulation layer comprises a thickness of about 100 microns (μ

m) or less.

15. The apparatus of claim 11, wherein the single substrate layer comprises a single layer of glass or a single layer of silicon.

16. The apparatus of claim 11, further comprising a cavity that substantially passes through the single substrate layer.

17. The apparatus of claim 11, wherein the means for passive functionality comprises an inductor.

18. The apparatus of claim 11, further comprising a second die coupled to the single substrate layer and the means for passive functionality.

19. The apparatus of claim 18, wherein the means for passive functionality comprises a first inductor and a second inductor, the first inductor coupled to the first die, and the second inductor coupled to the second die.

20. The apparatus of claim 11, wherein the apparatus is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

21. A method for fabricating a device, comprising:

providing a single substrate layer comprising a first surface and a second surface being substantially opposite to the first surface;

forming a plurality of interconnects over the first surface of the single substrate layer, wherein forming the plurality of interconnects forms interconnects that are configured to operate as at least one passive component;

coupling a first die to the single substrate layer and the plurality of interconnects; and

forming an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component;

forming a cavity in the single substrate such that the cavity passes through the second surface of the single substrate; and

forming a substrate interconnect (i) partially in the cavity of the single substrate layer such that the cavity is partially unfilled, and (ii) over the second surface of the single substrate layer such that the substrate interconnect travels at least laterally along the second surface of the single substrate, wherein the substrate interconnect is formed such that the substrate interconnect is coupled to the plurality of interconnects.

22. The method of claim 21, wherein the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μ

um) or less.

23. The method of claim 21, wherein the single substrate layer comprises a thickness of about 75 microns (μ

m) or less.

24. The method of claim 21, wherein the encapsulation layer comprises a thickness of about 100 microns (μ

m) or less.

25. The method of claim 21, wherein the single substrate layer comprises a single layer of glass or a single layer of silicon.

26. The method of claim 21, wherein forming the cavity comprises forming a cavity that substantially passes through the single substrate layer.

27. The method of claim 21, wherein the at least one passive component comprises an inductor.

28. The method of claim 21, further comprising coupling a second die to the single substrate layer and the plurality of interconnects.

29. The method of claim 21, further reducing the thickness of the single substrate layer.

30. The method of claim 21, wherein the package on package (PoP) device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.