Memory Cells and Memory Arrays

• US 20180061835A1
• Filed: 07/31/2017
• Published: 03/01/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yang, Gloria, Mathew, Suraj J., Singanamalla, Raghunath, Nair, Vinay, Derner, Scott J., Shore, Michael Amiel, Keeth, Brent, Simsek-Ege, Fatma Arzum, Tran, Diem Thy N.
• Granted Patent: US 10,157,926 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Claims

1. A memory cell, comprising:

first and second transistors; and

a capacitor vertically displaced relative to the first and second transistors, the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes.

2. The memory cell of claim 1 wherein the first and second transistors are in a common horizontal plane as one another.

3. The memory cell of claim 1 wherein the first and second transistors are not in a common horizontal plane as one another.

4. The memory cell of claim 1 wherein:

the first transistor has a first source/drain region and a second source/drain region, and the first node is electrically coupled with the first source/drain region;

the second transistor has a third source/drain region and a fourth source/drain region, and the second node is electrically coupled with the third source/drain region; and

the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

5. The memory cell of claim 1 wherein at least one of the first and second transistors has a gate configured to have at least one bent region, and one or more extension regions that extend along a channel region of said at least one of the first and second transistors from said at least one bent region;

and wherein the gate and the one or more extension regions together form a substantially T-shaped configuration, substantially shelf-shaped configuration or substantially U-shaped configuration.

6. A memory cell comprising:

first and second transistors laterally displaced relative to one another; and

a capacitor over the first and second transistors, the capacitor having an outer node electrically coupled with a source/drain region of the first transistor, having an inner node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the inner and outer nodes.

7. The memory cell of claim 6 wherein the outer node is container-shaped;

wherein the inner node extends into the container-shaped outer node over the first transistor; and

wherein a portion of the inner node extends outwardly of the container-shaped outer node, and extends to the source/drain region of the second transistor.

8. The memory cell of claim 6 wherein the first and second transistors are in a common horizontal plane, and wherein a common wordline extends to both of the first and second transistors and comprises gates of the first and second transistors.

9. The memory cell of claim 6 wherein:

the first transistor has a first source/drain region and a second source/drain region, and the outer node is electrically coupled with the first source/drain region;

the second transistor has a third source/drain region and a fourth source/drain region, and the inner node is electrically coupled with the third source/drain region; and

the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

10. The memory cell of claim 9 wherein the first and second comparative bitlines are in a common horizontal plane as one another.

11. A memory array comprising the memory cell of claim 10 as one memory cell within a plurality of memory cells;

wherein

an axis through the first and second comparative bitlines defines a mirror plane; and

another memory cell is on an opposing side of the mirror plane from said one memory cell and is substantially a mirror image of said one memory cell across the mirror plane;

said other memory cell sharing the first and second comparative bitlines with said one memory cell.

12. The memory cell of claim 9 wherein the first and second comparative bitlines are vertically displaced relative to one another.

13. The memory cell of claim 12 wherein the first and second comparative bitlines laterally overlap one another.

14. The memory cell of claim 12 wherein the first and second comparative bitlines do not laterally overlap one another.

15. A memory cell comprising:

first and second transistors vertically displaced relative to one another; and

a capacitor between the first and second transistors, the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes.

16. The memory cell of claim 15 wherein the first node is container-shaped and the second node extends into the first node, and wherein the first transistor is above the second transistor which in turn is above a semiconductor base.

17. The memory cell of claim 15 wherein the first node is container-shaped and the second node extends into the first node, and wherein the second transistor is above the first transistor which in turn is above a semiconductor base.

18. The memory cell of claim 15 wherein:

the first transistor has a first source/drain region and a second source/drain region, and the first node is electrically coupled with the first source/drain region;

the second transistor has a third source/drain region and a fourth source/drain region, and the second node is electrically coupled with the third source/drain region; and

the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

19. The memory cell of claim 18 wherein the first comparative bitline is above the first transistor and the second comparative bitline is below the second transistor.

20. The memory cell of claim 19 being in a memory array;

the first and second comparative bitlines being along a column of said memory array;

the memory cell being one of a plurality of substantially identical memory cells between the first and second comparative bitlines along said column.

21. An apparatus comprising a semiconductor base, a memory array including a plurality of memory cells, and an insulating film intervening between the semiconductor base and the plurality of memory cells;

wherein each of the memory cells comprises a first transistor, a second transistor and a capacitor; and

wherein each of the first transistor, the second transistor and the capacitor is formed over the insulating film covering the semiconductor base.

22. The apparatus of claim 21,

wherein the memory array further includes a plurality of pairs of bitlines and a plurality of wordlines, each of the memory cells being coupled to an associated one of the plurality of pairs of bitlines and an associated one of the plurality of wordlines, the first and second transistors and the capacitor being coupled in series between the associated one of the plurality of pairs of bitlines with the first and second transistors sandwiching the capacitor therebetween, and each of the first and second transistors being at a gate to the associated one of the plurality of wordlines.

23. The apparatus of claim 22,

wherein the associated one of the plurality of pairs of bitlines includes first and second bitlines;

wherein the insulating film includes a substantially planar surface; and

wherein the first and second bitlines are disposed on the substantially planar surface in parallel to each other.

24. The apparatus of claim 22,

wherein the associated one of the plurality of pairs of bitlines includes first and second bitlines;

wherein the insulating film includes a first surface and a second surface that is different in height from the first surface; and

wherein the first and second bitlines are on the first and second surfaces, respectively.

25. The apparatus of claim 24, wherein the first and second bitlines are formed such that respective portions of the first and second bitlines overlap with each other.

26. The apparatus of claim 22,

wherein each of the memory cells comprises the first and second semiconductor pillars extending vertically over the insulating film, the first semiconductor pillar including first and second portions serving as source and drain regions of the first transistor, respectively, and the second semiconductor pillar including third and fourth portions serving as source and drain regions of the second transistor, respectively.

27. The apparatus of claim 26,

wherein the associated one of the plurality of pairs of bitlines includes a first bitline and a second bitline, the first and second bitlines being laterally disposed with each other;

and

wherein the first and second semiconductor pillars are disposed over the first and second bitlines, respectively.

28. The apparatus of claim 26,

wherein the associated one of the plurality of pairs of bitlines includes a first bitline and a second bitline formed over the first bitline;

and

wherein the first and second semiconductor pillars are vertically aligned with each other between the first and second bitlines.