VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS
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Abstract
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
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Citations
28 Claims
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1-8. -8. (canceled)
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9. A semiconductor structure comprising at least:
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a substrate; at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate; a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers; a source region; a drain region; a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region. - View Dependent Claims (10, 12, 13, 14, 21, 22, 23, 24)
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11. (canceled)
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15. An integrated circuit comprising:
a semiconductor structure comprising at least; a substrate; at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate; a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers; a source region; a drain region; a first plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the first plurality of epitaxially grown interconnects contacts the source region and one semiconductor layer in the alternating stack, wherein the first plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the source region; and a second plurality of epitaxially grown interconnects, wherein each epitaxially grown interconnect in the second plurality of epitaxially grown interconnects contacts the drain region and one semiconductor layer in the alternating stack, wherein the second plurality of epitaxially grown interconnects forms an air pocket between each metal gate material layer in the alternating stack and the drain region. - View Dependent Claims (16, 18, 19, 20, 25, 26, 27, 28)
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17. (canceled)
Specification