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Digital Phase Locked Loop and Method for Operating the Same

  • US 20180062660A1
  • Filed: 08/28/2017
  • Published: 03/01/2018
  • Est. Priority Date: 08/30/2016
  • Status: Active Grant
First Claim
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1. A Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal, the DPLL comprising:

  • a phase detector configured for detecting a phase error of a feedback signal with respect to the reference clock signal, wherein the feedback signal is the output signal of the DPPL fed back to an input of the phase detector, wherein the phase detector comprises;

    an integer circuit configured for generating a first control signal representative of an integer phase error; and

    a fractional circuit comprising a Time-to-Digital Converter (TDC) configured for processing the feedback signal and a delayed reference clock signal to generate a TDC output, wherein the fractional circuit is configured for generating from the TDC output a second control signal representative of a fractional phase error;

    a digitally controlled oscillator (DCO) configured for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error detected by the phase detector; and

    an unwrapping unit configured for unwrapping the TDC output.

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