Digital Phase Locked Loop and Method for Operating the Same

• US 20180062660A1
• Filed: 08/28/2017
• Published: 03/01/2018
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: Stichting Imec Nederland
• Original Assignee: Stichting Imec Nederland
• Inventors: van den Heuvel, Johan, Liu, Yao-Hong
• Granted Patent: US 10,236,894 B2
• Time in Patent Office: Days
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Claims

1. A Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal, the DPLL comprising:

a phase detector configured for detecting a phase error of a feedback signal with respect to the reference clock signal, wherein the feedback signal is the output signal of the DPPL fed back to an input of the phase detector, wherein the phase detector comprises;

an integer circuit configured for generating a first control signal representative of an integer phase error; and

a fractional circuit comprising a Time-to-Digital Converter (TDC) configured for processing the feedback signal and a delayed reference clock signal to generate a TDC output, wherein the fractional circuit is configured for generating from the TDC output a second control signal representative of a fractional phase error;

a digitally controlled oscillator (DCO) configured for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error detected by the phase detector; and

an unwrapping unit configured for unwrapping the TDC output.

2. The DPLL of claim 1, comprising a processing unit configured for:

activating the integer circuit to obtain initial phase locking, and

deactivating the integer circuit when initial phase locking is obtained.

3. The DPLL of claim 1, wherein the unwrapping unit unwrapping the TDC output comprises shifting the TDC output when a change in the TDC output is larger than a predetermined limit value, wherein shifting the TDC output comprises shifting the TDC output by a predetermined unwrap value in a direction opposite of the change in the TDC output.

4. The DPLL of claim 3, wherein the unwrapping unit comprises:

a differentiator configured for differentiating subsequent TDC outputs;

a re-wrap unit configured for re-wrapping the differentiated TDC outputs by;

(a) adding the predetermined unwrap value to a negative differentiated TDC output when the negative differentiated TDC output has an absolute value larger than the predetermined limit value, or

(b) subtracting the predetermined unwrap value from a positive differentiated TDC output when the positive differentiated TDC output has an absolute value larger than the limit value; and

an integrator configured for integrating the re-wrapped differentiated TDC outputs to obtain unwrapped TDC outputs.

5. The DPLL of claim 3, wherein the predetermined limit value is a value of a gain of the TDC, and wherein the predetermined unwrap value is twice the value of the gain of the TDC.

6. The DPLL of claim 4, wherein the differentiator is further configured for leaking a predetermined amount of the TDC outputs to the differentiated TDC outputs.

7. The DPLL of claim 1, wherein the DPLL further comprises at least one calibration loop, wherein the unwrapping unit is configured for disabling the at least one calibration loop when the unwrapped TDC output is outside a predetermined range, and wherein the unwrapping unit is configured for re-enabling the at least one calibration loop when the unwrapped TDC output returns to within the predetermined range.

8. The DPLL of claim 7, wherein re-enabling the at least one calibration loop comprises re-enabling the at least one calibration loop after a predetermined period when the unwrapped TDC output returns to within the predetermined range.

9. The DPLL of claim 1, wherein the TDC has an increased out-of-range gain.

10. A method for operating a Digital Phase Locked Loop (DPLL) for phase locking an output signal of the DPLL to a reference clock signal, the method comprising:

supplying the reference clock signal to a first input of a phase detector of the DPLL;

supplying the output signal of the DPLL as a feedback signal to a second input of the phase detector;

generating, by an integer circuit of the phase detector, a first control signal representative of an integer phase error of the feedback signal with respect to the reference clock signal;

processing, by a Time-to-Digital Converter (TDC) of a fractional circuit of the phase detector, the feedback signal and a delayed reference clock signal to generate a TDC output;

generating from the TDC output a second control signal representative of a fractional phase error of the feedback signal with respect to the reference clock signal;

unwrapping the TDC output using an unwrapping unit of the DPLL;

regenerating the output signal of the DPLL using a digitally controlled oscillator (DCO) of the DPLL based at least on a frequency control word and at least one of the first control signal or the second control signal;

obtaining initial phase locking of the output signal of the DPLL to the reference clock signal by repeating (a) the supplying of the output signal as the feedback signal to the phase detector, (b) the generating of the first control signal, (c) the processing by the TDC, (d) the generating of the second control signal, (e) the unwrapping of the TDC output, and (f) the regenerating of the output signal of the DPLL;

deactivating the integer circuit of the phase detector after obtaining the initial phase locking; and

tracking the phase locking of the output signal of the DPLL to the reference clock signal by repeating (a) the supplying of the output signal as the feedback signal to the phase detector, (b) the processing by the TDC, (c) the generating of the second control signal, (d) the unwrapping of the TDC output, and (e) the regenerating of the output signal of the DPLL.

11. The method of claim 10, wherein deactivating the integer circuit of the phase detector comprises causing the integer circuit to no longer generate the first control signal representative of the integer phase error of the feedback signal with respect to the reference clock signal.

12. The method of claim 10, wherein unwrapping the TDC output comprises shifting the TDC output when a change in the TDC output is larger than a predetermined limit value, wherein shifting the TDC output comprises shifting the TDC output by a predetermined unwrap value in a direction opposite of the change in the TDC output.

13. The method of claim 12, wherein unwrapping the TDC output comprises:

differentiating subsequent TDC outputs;

re-wrapping the differentiated TDC outputs by;

(a) adding the predetermined unwrap value to a negative differentiated TDC output when the negative differentiated TDC output has an absolute value larger than the predetermined limit value, or

(b) subtracting the predetermined unwrap value from a positive differentiated TDC output when the positive differentiated TDC output has an absolute value larger than the predetermined limit value; and

integrating the re-wrapped differentiated TDC outputs to obtain unwrapped TDC outputs.

14. The method of claim 13, wherein the predetermined limit value is a value of a gain of the TDC, and wherein the predetermined unwrap value is twice the value of the gain of the TDC.

15. The method of claim 13, wherein differentiating subsequent TDC outputs comprises adding a predetermined amount of the TDC outputs to the differentiated TDC outputs.

16. The method of claim 10, wherein the DPLL comprises at least one calibration loop, the method further comprising:

disabling the at least one calibration loop when the unwrapped TDC output is outside a predetermined range; and

re-enabling the at least one calibration loop when the unwrapped TDC output returns to within the predetermined range.

17. The method of claim 16, wherein re-enabling the at least one calibration loop comprises re-enabling the at least one calibration loop after a predetermined period when the unwrapped TDC output returns to within the predetermined range.

18. The method of claim 10, further comprising increasing an out-of-range gain of the TDC by a processing unit of the DPLL.