MEMORY WEAR LEVELING

• US 20180067661A1
• Filed: 11/14/2017
• Published: 03/08/2018
• Est. Priority Date: 11/13/2014
• Status: Active Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fontana, Marco Giovanni, Montanaro, Massimo
• Application Number:
  US15/812,932
• Publication Number:
  US 20180067661A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.

Claims

1. A memory device, comprising:

a memory array of sectors having one or more sub-sectors;

wear-leveling logic configured to;

identify a target sector of the array of sectors having high wear, as determined based upon sub-sector information of one or more sub-sectors of the target sector; and

swap the target sector with a min sector of the memory device having a low wear level, as determined based upon sub-sector information of one or more sub-sectors of the min sector.

2. The memory device of claim 1, wherein the wear-leveling logic is configured to:

re-order a position of at least one sub-sector of the target sector, the min sector, or both.

3. The memory device of claim 2, wherein the wear-leveling logic is configured to:

re-order the position of the at least one sub-sector of the target sector prior to swapping the target sector with the min sector;

re-order the position of the at least one sub-sector of the min sector after swapping the target sector with the min sector;

or

both.

4. The memory device of claim 2, wherein the wear-leveling logic is configured to:

re-order the position of a high wear sub-sector by swapping the position of the high wear sub-sector.

5. The memory device of claim 1, wherein:

the sub-sector information of one or more sub-sectors of the target sector comprises a highest cycle count of a sub-sector of the target sector, a sum of sub-sector cycle counts for all sub-sectors of the target sector, an average of sub-sector cycle counts for all the sub-sectors of the target sector, or any combination thereof;

the sub-sector information of one or more sub-sectors of the min sector comprises a lowest cycle count of a sub-sector of the min sector, a sum of sub-sector cycle counts for all sub-sectors of the min sector, an average of sub-sector cycle counts for all the sub-sectors of the min sector, or any combination thereof;

or

both.

6. The memory device of claim 1, wherein the wear-leveling logic is configured to:

swap a position of a first bundle of two or more sub-sectors containing a high wear sub-sector with a position of a second bundle of two or more sub-sectors containing a low wear sub-sector.

7. The memory device of claim 1, wherein the memory device comprises a NAND type flash memory device, a NOR type flash memory device, or both.

8. The memory device of claim 1, comprising:

rescrambling logic configured to modify one or more intra-sector addresses of the memory array to re-order the position of the at least one sub-sector of the target sector, the min sector, or both.

9. The memory device of claim 8, comprising:

a block mapping unit configured to re-map one or more sectors, one or more sub-sectors, or both of the memory-array, wherein the block mapping unit is configured to provide configuration bits to the rescrambling logic to enable the modification of the one or more intra-sector addresses.

10. The memory device of claim 9, wherein the rescrambling logic comprises a multiplexer (MUX);

wherein the configuration bits comprise a plurality of sets of bits, each set of bits representing an address modification; and

wherein the MUX is configured to select one of the plurality of sets of bits, the selection resulting in an address modification represented by the selected one of the plurality of sets of bits.

11. The memory device of claim 9, wherein the rescrambling logic comprises combinational logic;

wherein the configuration bits comprise a single set of configuration bits; and

wherein the combinational logic affects a modification to an intra-sector address using the single set of configuration bits.

12. A method, comprising:

identifying a target sector of an array of sectors of a memory device that has high wear, as determined based upon sub-sector information of one or more sub-sectors of the target sector; and

swapping the target sector with a min sector of the memory device having a low wear level, as determined based upon the sub-sector information of the one or more sub-sectors of the min sector.

13. The method of claim 12, wherein:

the sub-sector information of one or more sub-sectors of the target sector comprises a highest cycle count of a sub-sector of the target sector, a sum of sub-sector cycle counts for all sub-sectors of the target sector, an average of sub-sector cycle counts for all the sub-sectors of the target sector, or any combination thereof;

the sub-sector information of the one or more sub-sectors of the min sector comprises a lowest cycle count of a sub-sector of the min sector, a sum of sub-sector cycle counts for all sub-sectors of the min sector, an average of sub-sector cycle counts for all the sub-sectors of the min sector, or any combination thereof;

or

both.

14. The method of claim 12, comprising:

determining a minimum sub-sector of the min sector having a minimum wear level; and

re-ordering a position of a high wear sub-sector of the target sector by swapping the position of the high wear sub-sector with a position of the minimum sub-sector.

15. The method of claim 12, comprising:

swapping a position of a first bundle of two or more sub-sectors containing a high wear sub-sector with a position of a second bundle of two more sub-sectors containing a low wear sub-sector.

16. The method of claim 12, comprising:

modifying one or more intra-sector addresses of the memory array to re-order a position of at least one sub-sector of the target sector, the min sector, or both.

17. The method of claim 16, comprising modifying the one or more intra-sector addresses of the memory array using:

a multiplexer;

combinational logic comprising summation logic, exclusive or (XOR) logic, or both;

or

both.

18. A memory controller, comprising:

circuitry configured to;

identify a target sector of the array of sectors having high wear, as determined based upon sub-sector information of one or more sub-sectors of the target sector; and

swap the target sector with a min sector of the memory device having a low wear level, as determined based upon sub-sector information of one or more sub-sectors of the min sector.

19. The memory controller of claim 18, wherein the circuitry is configured to re-order a position of at least one sub-sector while swapping the target sector with the min sector.

20. The memory controller of claim 18, wherein:

the sub-sector information of one or more sub-sectors of the target sector comprises a highest cycle count of a sub-sector of the target sector, a sum of sub-sector cycle counts for all sub-sectors of the target sector, an average of sub-sector cycle counts for all the sub-sectors of the target sector, or any combination thereof;

the sub-sector information of one or more sub-sectors of the min sector comprises a lowest cycle count of a sub-sector of the min sector, a sum of sub-sector cycle counts for all sub-sectors of the min sector, an average of sub-sector cycle counts for all the sub-sectors of the min sector, or any combination thereof;

or

both.