Devices, systems, and methods for increasing endurance on a storage system having a plurality of components using adaptive code-rates

• US 20180067666A1
• Filed: 09/06/2017
• Published: 03/08/2018
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Smart IOPS, Inc.
• Original Assignee: Smart IOPS, Inc.
• Inventors: d'Abreu, Manuel Antonio
• Granted Patent: US 10,423,345 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In certain aspects, devices, systems, and methods are provided for increasing endurance on a storage system having a plurality of components using adaptive code rates. A controller may be configured to receive a first data packet from a memory device; determine a bit error count for the first data packet; and determine whether the bit error count exceeds a predetermined threshold. When the bit error count exceeds the predetermined threshold, the controller corrects errors identified in the bit error count; generates and inserts pre-defined data into the first data packet at a location where errors occurred in the first data packet; and generates and inserts a tag into the first data packet. The tag includes information indicating a size and a location of the pre-defined data in the first data packet.

Claims

1. A data storage device, comprising:

a memory device comprising one or more memory dies; and

a controller communicatively coupled to the memory device and comprising logic to;

receive a first data packet from the memory device;

determine a bit error count for the first data packet;

determine whether the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correct errors identified in the bit error count;

generate pre-defined data and insert the pre-defined data into the first data packet at a location where errors occurred in the first data packet; and

generate a tag and insert the tag into the first data packet, the tag comprising information indicating a size and a location of the pre-defined data in the first data packet.

2. The data storage device of claim 1, wherein the first data packet is a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines.

3. The data storage device of claim 1, wherein the controller further comprises logic to:

move raw data comprising the corrected errors from the first data packet to a second data packet, when the error count is determined to exceed the predetermined threshold.

4. The data storage device of claim 1, wherein the controller further comprises logic to:

track bit error counts for the first data packet; and

reset the bit error count for the first data packet after the pre-defined data and the tag are inserted into the first data packet.

5. The data storage device of claim 1, wherein the tag further comprises decoding instructions.

6. The data storage device of claim 1, wherein the pre-defined data is a pattern of all 1'"'"'s or 0'"'"'s.

7. The data storage device of claim 1, wherein the controller further comprises logic to:

correct errors identified in the bit error count and update the bit error count for the first data packet, when the bit error count is determined to not exceed the predetermined threshold.

8. The data storage device of claim 1, wherein the predetermined threshold is a rate of increase of bit error counts, and wherein the bit error count is determined to exceed the predetermined threshold based on a comparison to a previous bit error count for the first data packet.

9. The data storage device of claim 1, wherein the memory device comprises a three-dimensional (3D) memory configuration.

10. The data storage device of claim 1, wherein the controller further comprises logic to:

classify one or more health levels for data packets;

maintain profile information for the data packets, the profile information comprising bit error counts for the data packets, wherein the data packets comprise the first data packet; and

determine the predetermined threshold for the first data packet based on the health level classifications.

11. A system, comprising:

a data storage device comprising;

a memory device; and

a controller communicatively coupled to the memory device, wherein the controller comprises logic to;

receive a first data packet from the memory device;

determine a bit error count for the first data packet;

determine whether the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correct errors identified in the bit error count;

generate pre-defined data and insert the pre-defined data into the first data packet at a location where errors occurred in the first data packet; and

generate a tag and insert the tag into the first data packet, the tag comprising information indicating a size and a location of the pre-defined data in the first data packet; and

an accessing device communicatively coupled to the data storage device, wherein the accessing device is configured to issue commands to the data storage device to read data from or write data to the memory device.

12. The system of claim 11, wherein the first data packet is a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines.

13. The system of claim 11, wherein the controller further comprises logic to:

track bit error counts for the first data packet;

move raw data comprising the corrected errors from the first data packet to a second data packet, when the error count is determined to exceed the predetermined threshold; and

reset the bit error count for the first data packet.

14. The system of claim 11, wherein the data storage device is embedded within the accessing device.

15. A method, comprising:

receiving, at a controller, a first data packet from a memory device, the memory device communicatively coupled to the controller;

determining, by the controller, a bit error count for the first data packet;

determining, by the controller, that the bit error count exceeds a predetermined threshold; and

when the bit error count is determined to exceed the predetermined threshold;

correcting, by the controller, errors identified in the bit error count;

generating, by the controller, pre-defined data and inserting, by the controller, the pre-defined data into the first data packet at a location where errors occurred in the first data packet; and

generating, by the controller, a tag and inserting, by the controller, the tag into the first data packet, wherein the tag comprises information indicating a size and a location of the pre-defined data in the first data packet.

16. The method of claim 15, wherein the first data packet is a wordline, block of wordlines, or a cluster of blocks of wordlines;

and wherein the pre-defined data and tag are inserted into the wordline, block of wordlines, or a cluster of blocks of wordlines.

17. The method of claim 15, further comprising:

moving, by the controller, raw data comprising the corrected errors from the first data packet to a second data packet, when the error count is determined to exceed the predetermined threshold.

18. The method of claim 15, further comprising:

tracking, by the controller, bit error counts for the first data packet; and

resetting, by the controller, the bit error count for the first data packet after the pre-defined data and the tag are inserted into the first data packet.

19. The method of claim 15, wherein the tag further comprises decoding instructions.

20. The method of claim 15, wherein the pre-defined data is a pattern of all 1'"'"'s or 0'"'"'s.