EFFICIENT DATA CACHING MANAGEMENT IN SCALABLE MULTI-STAGE DATA PROCESSING SYSTEMS

• US 20180067857A1
• Filed: 02/02/2017
• Published: 03/08/2018
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Wang, Jiayin, Yang, Zhengyu, Evans, Thomas David
• Granted Patent: US 10,452,612 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/124 being minimized, e.g. non MRU
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 16/172 Caching, prefetching or hoarding of files
• CPC Class Codes: G06F 16/188 Virtual file systems
• CPC Class Codes: G06F 2009/4557 Distribution of virtual machine instances; Migration and load balancing
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6024 History based prefetching
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/45558 : Hypervisor-specific management and integration aspects

Abstract

According to some example embodiments, a method includes: receiving, by a processor, from a data source, a processing profile comprising input data blocks and a plurality of operations for executing using the input data blocks; executing, by the processor, one or more of the operations of the processing profile to generate a new output data after each of the executed one or more operations; storing, by the processor, the new output data from at least one of the one or more operations as intermediate cache data; and transmitting, by the processor, the new output data from a final operation from among the one or more operations to the data source for display thereby.

Claims

1. A system comprising:

a processor; and

a memory coupled to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to;

receive, from a data source, a processing profile comprising input data blocks and a plurality of operations for executing using the input data blocks;

determine whether or not a block of stored intermediate cache data corresponds to an operation from among of the plurality of operations;

in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, generate a simplified processing profile based on the block of stored intermediate cache data;

execute the simplified processing profile by generating a new output data after each operation of the simplified processing profile;

store the new output data from at least one operation as intermediate cache data; and

transmit the output data from a final operation in the simplified processing profile to the data source for display thereby.

2. The system of claim 1, wherein the instructions further cause the processor to, in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, identify a location of the stored intermediate cache data among a plurality of worker nodes.

3. The system of claim 1, wherein generating the simplified processing profile comprises removing the operation corresponding to the block of stored intermediate cache data.

4. The system of claim 3, wherein the simplified processing profile comprises a subset of the plurality of operations of the processing profile without the operation corresponding to the block of stored intermediate cache data.

5. The system of claim 1, wherein the instructions further cause the processor to:

identify a candidate worker node from among a plurality of worker nodes for storing the new output data according to a load balance calculation of at least one of storage space of each of the worker nodes and input/output bandwidth of each of the worker nodes; and

store the new output data at the identified candidate worker node.

6. The system of claim 1, wherein the instructions further cause the processor to:

identify whether or not there is sufficient space among a plurality of worker nodes to store the new output data; and

in response to determining there is not sufficient space among the plurality of worker nodes, clear a block of pre-stored intermediate cache data having a lower priority level than the new output data.

7. A method comprising:

receiving, by a processor, from a data source, a processing profile comprising input data blocks and a plurality of operations for executing using the input data blocks;

determining, by the processor, whether or not a block of stored intermediate cache data corresponds to an operation from among of the plurality of operations;

in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, removing, by the processor, the operation from the processing profile to generate a simplified processing profile;

executing, by the processor, the simplified processing profile by generating a new output data after each operation of the simplified processing profile;

storing, by the processor, the new output data from at least one operation as intermediate cache data; and

transmitting, by the processor, the output data from a final operation in the simplified processing profile to the data source for display thereby.

8. The method of claim 7, further comprising, in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, identifying, by the processor, a location of the stored intermediate cache data among a plurality of worker nodes.

9. The method of claim 7, wherein generating the simplified processing profile comprises removing, by the processor, the operation corresponding to the block of stored intermediate cache data.

10. The method of claim 9, wherein the simplified processing profile comprises a subset of the plurality of operations of the processing profile without the operation corresponding to the block of stored intermediate cache data.

11. The method of claim 7, further comprising identifying, by the processor, a candidate worker node from among a plurality of worker nodes for storing the new output data according to a load balance calculation of at least one of storage space of each of the worker nodes and input/output bandwidth of each of the worker nodes.

12. The method of claim 11, further comprising storing, by the processor, the new output data at the identified candidate worker node.

13. The method of claim 7, further comprising:

identifying, by the processor, whether or not there is sufficient space among a plurality of worker nodes to store the new output data; and

in response to determining there is not sufficient space among the plurality of worker nodes, clearing, by the processor, a block of pre-stored intermediate cache data having a lower priority level than the new output data.

14. A method comprising:

receiving, by a processor, from a data source, a processing profile comprising input data blocks and a plurality of operations for executing using the input data blocks;

executing, by the processor, one or more of the operations of the processing profile to generate a new output data after each of the executed one or more operations;

storing, by the processor, the new output data from at least one of the one or more operations as intermediate cache data; and

transmitting, by the processor, the new output data from a final operation from among the one or more operations to the data source for display thereby.

15. The method of claim 14, further comprising:

determining, by the processor, whether or not a block of stored intermediate cache data corresponds to an operation from among of the plurality of operations; and

in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, removing, by the processor, the operation from the processing profile to generate a simplified processing profile.

16. The method of claim 15, further comprising, in response to determining the block of stored intermediate cache data corresponds to the operation from among the plurality of operations, identifying, by the processor, a location of the stored intermediate cache data among a plurality of worker nodes.

17. The method of claim 15, wherein the simplified processing profile comprises a subset of the plurality of operations of the processing profile without the operation corresponding to the block of stored intermediate cache data, and the method further comprises executing, by the processor, each of the plurality of operations among the subset.

18. The method of claim 14, further comprising identifying, by the processor, a candidate worker node from among a plurality of worker nodes for storing the new output data according to a load balance calculation of at least one of storage space of each of the worker nodes and input/output bandwidth of each of the worker nodes.

19. The method of claim 18, further comprising storing, by the processor, the new output data at the identified candidate worker node.

20. The method of claim 14, further comprising:

identifying, by the processor, whether or not there is sufficient space among a plurality of worker nodes to store the new output data; and

in response to determining there is not sufficient space among the plurality of worker nodes, clearing, by the processor, a block of pre-stored intermediate cache data having a lower priority level than the new output data.