MEMORY DEVICE
First Claim
1. A memory device comprising:
- a plurality of memory cells; and
a first word line connected to the memory cells,wherein when data is written,a first program voltage is applied to the first word line,a first verify voltage having at least one value is applied to the first word line to obtain a first verify result,a second program voltage is applied to the first word line,a second verify voltage having a same value as the at least one value is applied to the first word line to obtain a second verify result, andamong the memory cells, a first memory cell in which the first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.
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Abstract
According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.
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Citations
20 Claims
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1. A memory device comprising:
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a plurality of memory cells; and a first word line connected to the memory cells, wherein when data is written, a first program voltage is applied to the first word line, a first verify voltage having at least one value is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage having a same value as the at least one value is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell in which the first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18)
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12. A memory device comprising:
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first and second memory cells; and a first word line connected to the first and second memory cells, wherein in a write operation in which writing of first data into the first memory cell and writing of second data, which is different from the first data, into the second memory cell are started simultaneously, a first program voltage is applied to the first word line, a first verify voltage including a first determination level regarding the first data is applied to the first word line to obtain a first verify result, the first memory cell into which the first data has been written is set to a program inhibited state and a second program voltage to write the second data into the second memory cell is applied to the first word line after the writing of the first data is determined to be completed based on the first verify result, and a second verify voltage including a second determination level regarding the first data is applied to the first word line to obtain a second verify result. - View Dependent Claims (13, 14, 15, 16, 17)
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19. A memory device comprising:
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a first unit including a first memory cell and a second memory cell stacked above a semiconductor substrate; a second unit including a third memory cell and a fourth memory cell stacked above the semiconductor substrate; a first word line connected to the first memory cell and the third memory cell; and a second word line connected to the second memory cell and the fourth memory cell, wherein a first program voltage for a first program operation of the first memory cell is applied to the first word line, a second program voltage for a second program operation of the third memory cell is applied to the first word line after the first program voltage is applied to the first word line, a first verify voltage for a first verify operation of the first memory cell is applied to the first word line after the second program voltage is applied to the first word line, and a second verify voltage for a second verify operation of the third memory cell is applied to the first word line after the first verify voltage is applied to the first word line. - View Dependent Claims (20)
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Specification