MEMORY DEVICE

• US 20180068739A1
• Filed: 03/15/2017
• Published: 03/08/2018
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: SHIINO, Yasuhiro, NAKANO, Tomoaki, IRIEDA, Shigefumi, YOSHIDA, Masashi
• Granted Patent: US 10,049,760 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

Claims

1. A memory device comprising:

a plurality of memory cells; and

a first word line connected to the memory cells,

wherein when data is written,

a first program voltage is applied to the first word line,

a first verify voltage having at least one value is applied to the first word line to obtain a first verify result,

a second program voltage is applied to the first word line,

a second verify voltage having a same value as the at least one value is applied to the first word line to obtain a second verify result, and

among the memory cells, a first memory cell in which the first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

2. The device of claim 1, wherein when the second verify result of the first memory cell is a fail, a third program voltage is applied to the first word line to program the data into the first memory cell.

3. The device of claim 2, further comprising:

a first bit line connected to the first memory cell,

wherein a first voltage is applied to the first bit line when the first program voltage is applied,

a second voltage, which is higher than the first voltage, is applied to the first bit line when the second program voltage is applied, and

a third voltage, which is higher than the first voltage and lower than the second voltage, is applied to the first bit line when the third program voltage is applied.

4. The device of claim 3, wherein

after the third program voltage is applied,

a third verify voltage having a same value as the at least one value is applied to the first word line to obtain a third verify result, and

whether the first memory cell, which failed in the second verify result, passes in the third verify result is detected.

5. The device of claim 3, further comprising:

a first circuit capable of controlling a potential of the first bit line,

wherein the first circuit includes

a first transistor that supplies the first voltage to the first bit line when the first program voltage is applied,

a second transistor that supplies the second voltage to the first bit line when the second program voltage is applied, and

a third transistor that supplies the third voltage to the first bit line when the third program voltage is applied.

6. The device of claim 3, further comprising:

a first circuit capable of controlling a potential of the first bit line,

wherein the first circuit includes

a first transistor having a first terminal connected to the first bit line, a second terminal connected to a first interconnect, and a first gate,

a second transistor having a third terminal connected to the first interconnect and a fourth terminal connected to a first voltage terminal, and

a third transistor having a fifth terminal connected to the first interconnect and a sixth terminal connected to a second voltage terminal,

the first voltage is supplied to the first voltage terminal,

a fourth voltage equal to the third voltage or higher is supplied to the second voltage terminal,

when a first signal having a first signal level is supplied to the first gate, the first transistor supplies the first voltage from the second transistor to the first bit line,

when a second signal having a second signal level higher than the first signal level is supplied to the first gate, the first transistor supplies the second voltage to the first bit line using the fourth voltage from the third transistor, and

when a third signal having a third signal level higher than the first signal level and lower than the second signal level is supplied to the first gate, the first transistor supplies the third voltage to the first bit line using the fourth voltage from the third transistor.

7. The device of claim 1, further comprising:

a plurality of memory cells connected to a second word line,

wherein when the data is written,

a fourth program voltage is applied to the second word line after the first program voltage is applied to the first word line and before the first verify voltage is applied to the first word line.

8. The device of claim 7, wherein

a fourth verify voltage is applied to the second word line after the first verify voltage is applied and before the second program voltage is applied and

a fifth program voltage is applied to the second word line after the second program voltage is applied and before the second verify voltage is applied.

9. The device of claim 7, wherein

a fourth verify voltage is applied to the second word line after the first verify voltage is applied and before the second program voltage is applied and

a fifth program voltage is applied to the second word line after the fourth verify voltage is applied and before the second program voltage is applied.

10. The device of claim 1, wherein

the first verify voltage includes a first level and a second level higher than the first level and

when the first memory cell passes at the first level and fails at the second level, the first memory cell is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

11. The device of claim 1, wherein

the first verify result is based on a threshold of the memory cell by a program operation using the first program voltage and

the second verify result is based on the threshold of the memory cell by the program operation using the first program voltage and the program operation using the second program voltage.

18. The device of claim 1, further comprising:

a plurality of third memory cells connected to the first word line; and

a plurality of bit lines connected to each of the first memory cells and the third memory cells,

wherein completion of writing of the first data into the third memory cells is determined based on the first verify result,

a number of, among the first memory cells and the third memory cells, memory cells having a failed verify result is counted based on the second verify result,

a fourth voltage is applied to, among the bit lines, a plurality of second bit lines connected to the memory cells having the failed verify result when the number of the memory cells having the failed verify result is equal to a first number or less, and

a fifth voltage lower than the fourth voltage is applied to the second bit lines when the number of the memory cells having the failed verify result is larger than the first number.

12. A memory device comprising:

first and second memory cells; and

a first word line connected to the first and second memory cells,

wherein in a write operation in which writing of first data into the first memory cell and writing of second data, which is different from the first data, into the second memory cell are started simultaneously,

a first program voltage is applied to the first word line,

a first verify voltage including a first determination level regarding the first data is applied to the first word line to obtain a first verify result,

the first memory cell into which the first data has been written is set to a program inhibited state and a second program voltage to write the second data into the second memory cell is applied to the first word line after the writing of the first data is determined to be completed based on the first verify result, and

a second verify voltage including a second determination level regarding the first data is applied to the first word line to obtain a second verify result.

13. The device of claim 12, wherein

after the second verify voltage is applied, a third program voltage is applied to the first word line and

the first memory cell whose second verify result is a pass is set to a program inhibited state when the third program voltage is applied.

14. The device of claim 12, wherein

after the second verify voltage is applied, a third program voltage is applied to the first word line and

the first memory cell whose second verify result is a fail is set to a programmable state when the third program voltage is applied.

15. The device of claim 14, further comprising:

a first bit line connected to the first memory cell,

wherein a first voltage is applied to the first bit line when the first program voltage is applied,

a second voltage, which is higher than the first voltage, is applied to the first bit line when the second program voltage is applied, and

a third voltage, which is higher than the first voltage and lower than the second voltage, is applied to the first bit line when the third program voltage is applied.

16. The device of claim 12, wherein

a threshold voltage of the first memory cell holding the first data has a first value,

a threshold voltage of the second memory cell holding the second data has a second value higher than the first value, and

the first determination level is equal to the first value or less.

17. The device of claim 12, wherein

the second determination level is equal to the first determination level or less.

19. A memory device comprising:

a first unit including a first memory cell and a second memory cell stacked above a semiconductor substrate;

a second unit including a third memory cell and a fourth memory cell stacked above the semiconductor substrate;

a first word line connected to the first memory cell and the third memory cell; and

a second word line connected to the second memory cell and the fourth memory cell,

wherein

a first program voltage for a first program operation of the first memory cell is applied to the first word line,

a second program voltage for a second program operation of the third memory cell is applied to the first word line after the first program voltage is applied to the first word line,

a first verify voltage for a first verify operation of the first memory cell is applied to the first word line after the second program voltage is applied to the first word line, and

a second verify voltage for a second verify operation of the third memory cell is applied to the first word line after the first verify voltage is applied to the first word line.

20. The device of claim 19, further comprising:

a first select transistor included in the first unit, the first transistor including a first terminal connected to the first memory cell and a second terminal connected a first bit line;

a second select transistor included in the second unit, the second transistor including a third terminal connected to the third memory cell and a second terminal connected a second bit line;

a first select gate line connected to a first gate electrode of the first select transistor; and

a second select gate line connected to a second gate electrode of the second select transistor,

wherein

a first voltage is applied to the first select gate line and a second voltage lower than the first voltage is applied to the second select gate line while the first program voltage is applied to the first word line,

the second voltage is applied to the first select gate line and the first voltage is applied to the second select gate line while the second program voltage is applied to the first word line,

the first voltage is applied to the first select gate line and the second voltage is applied to the second select gate line while the first verify voltage is applied to the first word line, and

the second voltage is applied to the first select gate line and the first voltage is applied to the second select gate line while the second verify voltage is applied to the third word line.