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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

  • US 20180068740A1
  • Filed: 06/16/2017
  • Published: 03/08/2018
  • Est. Priority Date: 09/06/2016
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell array including a plurality of memory cells;

    a read/write circuit configured to write data to the memory cell array or read data from the memory cell array; and

    a control logic configured to control the read/write circuit to perform a read/write operation for the memory cell array,wherein the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks, andwherein, during an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.

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