SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
First Claim
1. A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells;
a read/write circuit configured to write data to the memory cell array or read data from the memory cell array; and
a control logic configured to control the read/write circuit to perform a read/write operation for the memory cell array,wherein the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks, andwherein, during an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.
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Accused Products
Abstract
A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to write data to the memory cell array or read data from the memory cell array. The control logic is configured to control the read/write circuit to perform a read/write operation for the memory cell array. The memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks. During an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.
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Citations
17 Claims
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1. A semiconductor memory device comprising:
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a memory cell array including a plurality of memory cells; a read/write circuit configured to write data to the memory cell array or read data from the memory cell array; and a control logic configured to control the read/write circuit to perform a read/write operation for the memory cell array, wherein the memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks, and wherein, during an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for operating a semiconductor memory device including a plurality of memory blocks each of which is divided into a plurality of sub-blocks, the method comprising:
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determining a target memory block to be erased; determining a target sub-block to be erased in the determined memory block; determining an erase verify voltage of the determined sub-block; and erasing the determined sub-block using the determined erase verify voltage. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification