SEMICONDUCTOR DEVICES INCLUDING TRAP RICH LAYER REGIONS

• US 20180069079A1
• Filed: 09/02/2016
• Published: 03/08/2018
• Est. Priority Date: 09/02/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Fanelli, Steve, Hammond, Richard
• Application Number:
  US15/255,744
• Publication Number:
  US 20180069079A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface

Abstract

In a particular aspect, a device includes a substrate including a first trap rich layer region and a second trap rich layer region. The first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate. The device further includes a semiconductor device layer including one or more components.

Claims

1. A device comprising:

a substrate comprising a first trap rich layer region and a second trap rich layer region, wherein the first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate; and

a semiconductor device layer including one or more components, the one or more components including a first component, wherein the first component is aligned with at least a portion of the first trap rich layer region.

2. The device of claim 1, wherein the first trap rich layer region and the second trap rich layer region comprise high resistance polysilicon, and wherein the first trap rich layer region and the second trap rich layer region each include electrically active charge carrier traps.

3. The device of claim 1, wherein the substrate further comprises a buried oxide (BOX) layer located between the first trap rich layer region and the semiconductor device layer.

4. The device of claim 3, wherein a surface of the first trap rich layer region is in direct contact with the BOX layer.

5. The device of claim 1, wherein the substrate further comprises a laser stop layer located between the first trap rich layer region and the semiconductor device layer, the laser stop layer including at least one dopant.

6. The device of claim 5, wherein a surface of the first trap rich layer region is in direct contact with the laser stop layer.

7. The device of claim 5, wherein the at least one dopant includes germanium.

8. The device of claim 5, wherein the at least one dopant includes carbon.

9. The device of claim 1, wherein the first trap rich layer region and the second trap rich layer region include implanted ions.

10. The device of claim 1, the substrate further comprising:

a first silicon layer of the substrate located between the semiconductor device layer and the first trap rich layer region; and

a second silicon layer of the substrate, wherein the first trap rich layer region is located between the first silicon layer and the second silicon layer, and wherein the first trap rich layer region has a rough interface with the second silicon layer.

12. The device of claim 10, wherein the one or more components include a transistor, a radio frequency (RF) core, or a combination thereof, and wherein the first silicon layer is located between the first trap rich layer region and a gate of the transistor, and wherein the first silicon layer is located between the second trap rich layer region and the RF core.

14. The device of claim 1, wherein the substrate and the semiconductor device layer are integrated in a transceiver, and wherein the transceiver is included in a mobile device.

15. The device of claim 1, wherein the substrate and the semiconductor device layer are integrated in a transceiver, and wherein the transceiver is included in a base station.

31. The device of claim 1, wherein the first component comprises a transistor, and wherein a gate of the transistor is aligned with the first trap rich layer region with respect to a first direction, the first direction orthogonal to a second direction along an interface between the first trap rich layer region and a second silicon layer of the substrate.

32. The device of claim 1, wherein the first component comprises a radio frequency (RF) core, and wherein the RF core is aligned with the first trap rich layer region with respect to a first direction, the first direction orthogonal to a second direction along an interface between the first trap rich layer region and a second silicon layer of the substrate.

33. The device of claim 1, wherein the portion of the substrate that separates the first trap rich layer region from the second trap rich layer region comprises a portion of an ion implant trapper layer of the substrate.

11. (canceled)

13. (canceled)

16. A method of semiconductor fabrication, the method comprising:

forming a first trap rich layer region within a first region of a substrate during a first portion of an energy application process; and

forming a second trap rich layer region within a second region of the substrate during a second portion of the energy application process, wherein the first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate.

17. The method of claim 16, wherein the energy application process is performed using a laser or using an ion beam.

19. The method of claim 16, further comprising forming an ion implant trapper layer in the substrate prior to forming the first trap rich layer region and the second trap rich layer region, wherein the first trap rich layer region and the second trap rich layer region are formed within the ion implant trapper layer.

20. The method of claim 16, further comprising forming one or more components of a semiconductor device layer on the substrate prior to forming the first trap rich layer region and the second trap rich layer region, the one or more components including a first component, wherein the first component is aligned with at least a portion of the first trap rich layer region.

21. The method of claim 20, wherein the semiconductor device layer is formed on a first surface of the substrate, and wherein energy is applied through an opposite surface of the substrate during the energy application process.

22. The method of claim 20, wherein the semiconductor device layer is formed on a first surface of the substrate, and wherein energy is applied through the first surface of the substrate during the energy application process.

18. (canceled)

23. A method of semiconductor fabrication, the method comprising:

forming one or more components of a semiconductor device layer on a first surface of a substrate; and

forming a trap rich layer within the substrate by applying energy through a second surface of the substrate, wherein the second surface is opposite to the first surface.

24. The method of claim 23, wherein the trap rich layer is formed using a stealth dicing laser.

25. The method of claim 24, further comprising, prior to forming the trap rich layer, forming a laser stop layer within the substrate by implanting one or more dopants within the substrate.

26. The method of claim 23, wherein the trap rich layer is formed using an ion beam.

27. The method of claim 23, wherein forming the trap rich layer comprises:

applying energy through a first region of the second surface to form a first trap rich layer region, wherein the one or more components include a first component, wherein the first component is aligned with at least a portion of the first trap rich layer region;

applying energy through a second region of the second surface to form a second trap rich layer region, wherein the first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate; and

applying energy through a third region of the second surface to form a third trap rich layer region, wherein the first trap rich layer region is separated from the third trap rich layer region by a second portion of the substrate.

28. A method of semiconductor fabrication, the method comprising:

forming a laser stop layer within a substrate; and

applying a laser to the substrate to form a trap rich layer within the substrate.

29. The method of claim 28, wherein forming the trap rich layer comprises:

applying the laser to a first region of the substrate to form a first trap rich layer region; and

applying the laser to a second region of the substrate to form a second trap rich layer region, wherein the first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate.

30. The method of claim 28, wherein forming the laser stop layer comprises implanting one or more dopants within the substrate, wherein the one or more dopants include germanium, carbon, or a combination thereof.