AGGREGATED METADATA TRANSFER AT A DATA STORAGE DEVICE

• US 20180069658A1
• Filed: 04/21/2017
• Published: 03/08/2018
• Est. Priority Date: 09/07/2016
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: BENISTY, SHAY, WEINBERG, YOAV
• Granted Patent: US 10,069,597 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A memory control circuit includes a metadata aggregate buffer configured to store a first plurality of consecutive metadata packets. The memory control circuit also includes control circuitry configured to send aggregated metadata to a memory via a first packet. The aggregated metadata includes at least two metadata packets of the first plurality of consecutive metadata packets.

Claims

1. A memory control circuit comprising:

a metadata aggregate buffer configured to store a first plurality of consecutive metadata packets; and

control circuitry configured to send aggregated metadata to a memory via a first packet, the aggregated metadata including at least two metadata packets of the first plurality of consecutive metadata packets.

2. The memory control circuit of claim 1, wherein the first plurality of consecutive metadata packets includes error correction code (ECC) data, cyclical redundancy check (CRC) data, parity data, data integrity information, data protection information, or a combination thereof.

3. The memory control circuit of claim 1, further comprising a data buffer configured to store a plurality of consecutive data packets, wherein the plurality of consecutive data packets is associated with the first plurality of consecutive metadata packets.

4. The memory control circuit of claim 1, wherein the control circuitry is further configured to receive second aggregated metadata from the memory via a second packet, the second aggregated metadata including a second plurality of consecutive metadata packets, and wherein the control circuitry is further configured to store the second plurality of consecutive metadata packets at the metadata aggregate buffer.

5. The memory control circuit of claim 4, further comprising an error correction code (ECC) engine configured to decode a data packet based on a corresponding metadata packet of the second plurality of consecutive metadata packets.

6. The memory control circuit of claim 1, wherein the memory is integrated within an access device, and wherein the metadata aggregate buffer and the control circuitry are integrated within a data storage device coupled to the access device.

7. The memory control circuit of claim 1, wherein the memory is integrated within a data storage device, and wherein the metadata aggregate buffer and the control circuitry are integrated within a controller of the data storage device.

8. The memory control circuit of claim 1, wherein the control circuitry is configured to receive one or more metadata packets of the first plurality of consecutive metadata packets out of order and to store the one or more metadata packets in order at the metadata aggregate buffer.

9. The memory control circuit of claim 1, wherein the memory comprises a metadata buffer.

10. A method comprising:

buffering, at a metadata aggregate buffer, a plurality of consecutive metadata packets that includes a first metadata packet and a second metadata packet;

aggregating the first metadata packet and the second metadata packet to generate aggregated metadata; and

sending the aggregated metadata to a memory via a first packet.

11. The method of claim 10, further comprising packetizing the aggregated metadata in a single packet, the single packet comprising the first packet.

12. The method of claim 10, further comprising:

aggregating a third metadata packet of the plurality of consecutive metadata packets and a fourth metadata packet of the plurality of consecutive metadata packets to generate second aggregated metadata; and

sending the second aggregated metadata to the memory via a second packet.

13. The method of claim 10, further comprising generating the aggregated metadata in response to expiration of a particular time period that begins at receipt of the first metadata packet.

14. The method of claim 10, further comprising generating the aggregated metadata in response to a count of metadata packets associated with the plurality of consecutive metadata packets satisfying a threshold.

15. The method of claim 10, further comprising:

receiving a third metadata packet at the metadata aggregate buffer;

generating the aggregated metadata in response to determining that the third metadata packet is non-consecutive with respect to the plurality of consecutive metadata packets; and

sending the third metadata packet to the memory after sending the aggregated metadata.

16. The method of claim 15, further comprising determining that the third metadata packet is non-consecutive with respect to the plurality of consecutive metadata packets in response to a size associated with the third metadata packet being different from a size associated with each of the plurality of consecutive metadata packets.

17. An apparatus comprising:

first means for buffering a first plurality of consecutive metadata packets; and

first means for aggregating the first plurality of consecutive metadata packets to generate aggregated metadata and for sending the aggregated metadata via a first packet to first means for storing metadata.

18. The apparatus of claim 17, further comprising:

second means for buffering a second plurality of consecutive metadata packets; and

second means for aggregating the second plurality of consecutive metadata packets to generate second aggregated metadata and for sending the second aggregated metadata via a second packet to second means for storing metadata.

19. The apparatus of claim 18, further comprising means for decoding a first data packet based on a first metadata packet of the first plurality of consecutive metadata packets and for decoding a second data packet based on a second metadata packet of the second plurality of consecutive metadata packets.

20. The apparatus of claim 17, further comprising means for coupling the first means for aggregating to the first means for storing metadata, wherein a bandwidth associated with the first means for coupling is greater than a size of a first metadata packet of the first plurality of consecutive metadata packets.