CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES

• US 20180069735A1
• Filed: 09/08/2017
• Published: 03/08/2018
• Est. Priority Date: 09/08/2016
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Sharpe-Geisler, Bradley
• Granted Patent: US 10,326,627 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 2027/0036 using a recovered symbol clock
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657

Abstract

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Claims

1. A method comprising:

receiving a serial data stream;

measuring payload time periods between signal transitions in a payload portion of the serial data stream using at least one Grey code oscillator; and

generating a recovered data signal corresponding to the payload portion of the serial data stream by, at least in part, comparing the measured payload time periods to one or more calibration time periods.

2. The method of claim 1, wherein the measuring the payload time periods comprises:

incrementing, by the Grey code oscillator, a Grey code count between the signal transitions in the payload portion of the serial data stream; and

converting the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to one of the payload time periods.

3. The method of claim 1, wherein the Grey code oscillator comprises a first Grey code oscillator, and wherein the measuring the payload time periods comprises:

incrementing, by the first Grey code oscillator, a first Grey code count from zero between negative and adjacent positive signal transitions in the payload portion of the serial data stream;

converting the first Grey code count approximately at the adjacent positive signal transitions to a plurality of low binary counts corresponding to low payload time periods between the negative and adjacent positive signal transitions;

incrementing, by a second Grey code oscillator, a second Grey code count from zero between positive and adjacent negative signal transitions in the payload portion of the serial data stream; and

converting the second Grey code count approximately at the adjacent negative signal transitions to a plurality of high binary counts corresponding to high payload time periods between the positive and adjacent negative signal transitions.

4. The method of claim 3, wherein the generating the recovered data signal comprises, for each pair of adjacent low and high time periods of the payload portion of the serial data stream:

comparing the corresponding low binary count to one or more low calibration binary counts and/or data patterns to identify a corresponding low data pattern associated with the pair of the adjacent low and high time periods;

comparing the corresponding high binary count to one or more high calibration binary counts and/or data patterns to identify a corresponding high data pattern associated with the pair of the adjacent low and high time periods; and

combining the low and high data patterns to form a portion of the recovered data signal corresponding to the pair of adjacent low and high time periods.

5. The method of claim 1, wherein the generating the recovered data signal comprises:

generating a recovered clock signal corresponding to the serial data stream by, at least in part, comparing the measured payload time periods to a base calibration time period and initiating a recovered clock signal transition when the measured payload time period exceeds the base calibration time period; and

generating the recovered data signal by sampling the payload portion of the serial data stream at the recovered clock signal transitions.

6. The method of claim 1, wherein the payload portion of the serial data stream comprises an encoded data stream and the recovered data signal comprises a corresponding encoded data signal, the method further comprising:

decoding the recovered data signal into an eight bit encoded data signal.

7. The method of claim 1, further comprising:

detecting a training portion in a preamble of the serial data stream;

generating one or more calibration serial data streams based, at least in part, on the training portion of the serial data stream;

measuring the one or more calibration time periods between calibration signal transitions in the corresponding one or more calibration serial data streams using the at least one Grey code oscillator; and

storing the one or more calibration time periods in corresponding one or more storage registers.

8. The method of claim 7, wherein the measuring the one or more calibration time periods comprises:

incrementing, by the Grey code oscillator, a Grey code count between the calibration signal transitions in the corresponding one or more calibration serial data streams; and

converting the Grey code count approximately at the calibration signal transitions to a plurality of calibration binary counts each corresponding to one of the one or more calibration time periods.

9. The method of claim 7, wherein the Grey code oscillator comprises a first Grey code oscillator, and wherein the measuring the one or more calibration time periods comprises:

incrementing, by the first Grey code oscillator, a first Grey code count from zero between negative and adjacent positive signal transitions in the corresponding one or more calibration serial data streams;

converting the first Grey code count approximately at the adjacent positive signal transitions to a plurality of low calibration binary counts corresponding to the one or more calibration time periods between the negative and adjacent positive signal transitions;

incrementing, by the second Grey code oscillator, a second Grey code count from zero between positive and adjacent negative signal transitions in the corresponding one or more calibration serial data streams; and

converting the second Grey code count approximately at the adjacent negative signal transitions to a plurality of high calibration binary counts corresponding to the one or more calibration time periods between the positive and adjacent negative signal transitions.

10. A computer-implemented method comprising:

detecting, in a design for a programmable logic device (PLD), a serial data stream input and a deserializer block configured to generate a recovered data signal corresponding to a payload portion of a serial data stream provided by the serial data stream input; and

synthesizing the design into a plurality of PLD components, wherein the plurality of PLD components are configured to implement;

a Grey code oscillator for the deserializer block in the design, wherein the Grey code oscillator is configured to measure payload time periods between signal transitions in the payload portion of the serial data stream provided by the serial data stream input; and

at least one comparator for the deserializer block in the design, wherein the at least one comparator is configured to compare the measured payload time periods provided by the Grey code oscillator to one or more calibration time periods to generate the recovered data signal.

11. The computer-implemented method of claim 10, wherein the plurality of PLD components are further configured to implement:

a Grey code converter for the deserializer block in the design, wherein the Grey code converter is configured to convert a Grey code count provided by the Grey code oscillator approximately at the signal transitions to a plurality of binary counts each corresponding to one of the payload time periods.

12. The computer-implemented method of claim 10, wherein the plurality of PLD components are further configured to implement:

at least one storage register for the deserializer block in the design, wherein the at least one storage register is configured to store one or more calibration binary counts corresponding to the one or more calibration time periods and provide the one or more calibration binary counts to the at least one comparator.

13. The computer-implemented method of claim 10, wherein the payload portion of the serial data stream comprises an encoded data stream and the recovered data signal comprises a corresponding encoded data signal, wherein the plurality of PLD components are further configured to implement:

a decoder for the deserializer block in the design, wherein the decoder is configured to decode the recovered data signal into an eight bit encoded data signal.

14. The computer-implemented method of claim 10, wherein the plurality of PLD components are further configured to implement:

a data recovery circuit for the deserializer block in the design, comprising the at least one comparator, wherein the data recovery circuit is configured to receive the one or more calibration time periods and the measured payload time periods and generate a recovered data signal corresponding to the serial data stream, and wherein the recovered data signal is based, at least in part, on the change in the output state of the at least one comparator.

15. The computer-implemented method of claim 10, wherein the plurality of PLD components are further configured to implement:

a calibration signal generator for the deserializer block in the design, wherein the calibration signal generator is configured to detect a training portion in a preamble of the serial data stream and/or generate one or more calibration serial data streams based, at least in part, on the training portion of the serial data stream.

16. The computer-implemented method of claim 10, wherein the Grey code oscillator comprises a first Grey code oscillator, and wherein the plurality of PLD components are further configured to implement:

a second Grey code oscillator for the deserializer block in the design, wherein the first Grey code oscillator is configured to increment a first Grey code count from zero between negative and adjacent positive signal transitions in the payload portion of the serial data stream, and the second Grey code oscillator is configured to increment a second Grey code count from zero between positive and adjacent negative signal transitions in the payload portion of the serial data stream.

17. The computer-implemented method of claim 16, wherein:

the first and/or second Grey code oscillators are each implemented entirely within a programmable logic block of the PLD.

18. The computer-implemented method of claim 10, further comprising:

receiving the design;

routing connections between the plurality of PLD components;

generating configuration data to configure physical components of the PLD in accordance with the plurality of PLD components and a routing for the design; and

programming the PLD with the configuration data.

19. A PLD comprising configuration data comprising the plurality of PLD components synthesized according to the computer-implemented method of claim 10.

20. A system to perform the computer-implemented method of claim 10, the system comprising:

a processor; and

a memory adapted to store a plurality of computer readable instructions which when executed by the processor are adapted to cause the system to perform the computer-implemented method of claim 10.