METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COMPUTER PROCESSOR BASED ON PROGRAM PHASE

• US 20180074568A1
• Filed: 11/15/2017
• Published: 03/15/2018
• Est. Priority Date: 01/04/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: PRIYADARSHI, Shivam, KRISHNA, Anil, DAMODARAN, Raguram, BRIDGES, Jeffrey Todd, WELLS, Ryan, GARGASH, Norman, SMITH, Rodney Wayne
• Granted Patent: US 10,551,896 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Claims

1. A method for dynamic clock and voltage scaling, comprising:

configuring a polling interval for defining a current program execution phase;

measuring a stall fraction for the current program execution phase according to the configured polling interval, wherein the measured stall fraction indicates a degree to which the current program execution phase was memory-bound due at least in part to a processor waiting on data from a memory subsystem;

predicting a stall fraction for a next program execution phase based on the measured stall fraction for the current program execution phase in combination with a predicted stall fraction for the current program execution phase; and

applying, by the processor, a frequency setting and a voltage setting for the next program execution phase based on the predicted stall fraction for the next program execution phase.

2. The method recited in claim 1, wherein the measured stall fraction further indicates the degree to which the current program execution phase was memory-bound due to the processor not performing useful work while waiting on the data from the memory subsystem.

3. The method recited in claim 1, wherein the stall fraction for the next program execution phase is predicted according to a moving average based on the measured stall fraction and the predicted stall fraction for the current program execution phase.

4. The method recited in claim 3, wherein the moving average is an exponential moving average calculated according to the formula:

PredStall_n+1=α

*Stall_n+(1−

α

)*PredStall_n,

where α

is a constant value, Stall_n is the measured stall fraction for the current program execution phase, and PredStall_n is the predicted stall fraction for the current program execution phase.

5. The method recited in claim 1, wherein the predicted stall fraction for the current program execution phase is calculated in a preceding program execution phase.

6. The method recited in claim 1, wherein the frequency setting and the voltage setting to be applied during the next program execution phase is mapped to the predicted stall fraction for the next program execution phase.

7. The method recited in claim 1, further comprising:

comparing the predicted stall fraction for the next program execution phase to multiple different thresholds that correspond to different frequency and voltage setting combinations; and

mapping the predicted stall fraction for the next program execution phase to one of the multiple different frequency and voltage setting combinations that has a maximum power savings, a minimum performance loss, or a combination thereof at the predicted stall fraction.

8. The method recited in claim 1, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which a dispatch stall occurred.

9. The method recited in claim 1, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which an oldest instruction in a load queue was a last-level cache miss.

10. The method recited in claim 1, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based on a number of cycles during the current program execution phase in which a dispatch stall occurred while an oldest instruction in a load queue was a last-level cache miss.

11. An apparatus, comprising:

a memory subsystem; and

a processor coupled to the memory subsystem, the processor configured to;

configure a polling interval for defining a current program execution phase;

measure a stall fraction for the current program execution phase according to the configured polling interval, wherein the measured stall fraction indicates a degree to which the current program execution phase was memory-bound due at least in part to the processor waiting on data from the memory subsystem;

predict a stall fraction for a next program execution phase based on the measured stall fraction for the current program execution phase in combination with a predicted stall fraction for the current program execution phase; and

apply a frequency setting and a voltage setting for the next program execution phase based on the predicted stall fraction for the next program execution phase.

12. The apparatus recited in claim 11, wherein the measured stall fraction further indicates the degree to which the current program execution phase was memory-bound due to the processor not performing useful work while waiting on the data from the memory subsystem.

13. The apparatus recited in claim 11, wherein the processor is configured to predict the stall fraction for the next program execution phase according to a moving average based on the measured stall fraction and the predicted stall fraction for the current program execution phase.

14. The apparatus recited in claim 13, wherein the moving average is an exponential moving average calculated according to the formula:

PredStall_n+1=α

*Stall_n+(1−

α

)*PredStall_n,

where α

is a constant value, Stall_n is the measured stall fraction for the current program execution phase, and PredStall_n is the predicted stall fraction for the current program execution phase.

15. The apparatus recited in claim 11, wherein the processor is further configured to calculate the predicted stall fraction for the current program execution phase in a preceding program execution phase.

16. The apparatus recited in claim 11, wherein the frequency setting and the voltage setting to be applied during the next program execution phase is mapped to the predicted stall fraction for the next program execution phase.

17. The apparatus recited in claim 11, wherein the processor is further configured to:

compare the predicted stall fraction for the next program execution phase to multiple different thresholds that correspond to different frequency and voltage setting combinations; and

map the predicted stall fraction for the next program execution phase to one of the multiple different frequency and voltage setting combinations that has a maximum power savings, a minimum performance loss, or a combination thereof at the predicted stall fraction.

18. The apparatus recited in claim 11, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which a dispatch stall occurred.

19. The apparatus recited in claim 11, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which an oldest instruction in a load queue was a last-level cache miss.

20. The apparatus recited in claim 11, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based on a number of cycles during the current program execution phase in which a dispatch stall occurred while an oldest instruction in a load queue was a last-level cache miss.

21. An apparatus, comprising:

means for configuring a polling interval for defining a current program execution phase;

means for measuring a stall fraction for the current program execution phase according to the configured polling interval, wherein the measured stall fraction indicates a degree to which the current program execution phase was memory-bound due at least in part to a processor waiting on data from a memory subsystem;

means for predicting a stall fraction for a next program execution phase based on the measured stall fraction for the current program execution phase in combination with a predicted stall fraction for the current program execution phase; and

means for applying a frequency setting and a voltage setting for the next program execution phase based on the predicted stall fraction for the next program execution phase.

22. The apparatus recited in claim 21, wherein the measured stall fraction further indicates the degree to which the current program execution phase was memory-bound due to the processor not performing useful work while waiting on the data from the memory subsystem.

23. The apparatus recited in claim 21, wherein the stall fraction for the next program execution phase is predicted according to a moving average based on the measured stall fraction and the predicted stall fraction for the current program execution phase.

24. The apparatus recited in claim 23, wherein the moving average is an exponential moving average calculated according to the formula:

PredStall_n+1=α

*Stall_n+(1−

α

)*PredStall_n,

where α

is a constant value, Stall_n is the measured stall fraction for the current program execution phase, and PredStall_n is the predicted stall fraction for the current program execution phase.

25. The apparatus recited in claim 21, wherein the predicted stall fraction for the current program execution phase is calculated in a preceding program execution phase.

26. The apparatus recited in claim 21, wherein the frequency setting and the voltage setting to be applied during the next program execution phase is mapped to the predicted stall fraction for the next program execution phase.

27. The apparatus recited in claim 21, further comprising:

means for comparing the predicted stall fraction for the next program execution phase to multiple different thresholds that correspond to different frequency and voltage setting combinations; and

means for mapping the predicted stall fraction for the next program execution phase to one of the multiple different frequency and voltage setting combinations that has a maximum power savings, a minimum performance loss, or a combination thereof at the predicted stall fraction.

28. The apparatus recited in claim 21, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which a dispatch stall occurred.

29. The apparatus recited in claim 21, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which an oldest instruction in a load queue was a last-level cache miss.

30. The apparatus recited in claim 21, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based on a number of cycles during the current program execution phase in which a dispatch stall occurred while an oldest instruction in a load queue was a last-level cache miss.

31. A non-transitory computer-readable medium, wherein the non-transitory computer-readable medium comprises code for causing a processor to:

configure a polling interval for defining a current program execution phase;

measure a stall fraction for the current program execution phase according to the configured polling interval, wherein the measured stall fraction indicates a degree to which the current program execution phase was memory-bound due at least in part to the processor waiting on data from a memory subsystem;

predict a stall fraction for a next program execution phase based on the measured stall fraction for the current program execution phase in combination with a predicted stall fraction for the current program execution phase; and

apply a frequency setting and a voltage setting for the next program execution phase based on the predicted stall fraction for the next program execution phase.

32. The non-transitory computer-readable medium recited in claim 31, wherein the measured stall fraction further indicates the degree to which the current program execution phase was memory-bound due to the processor not performing useful work while waiting on the data from the memory subsystem.

33. The non-transitory computer-readable medium recited in claim 31, wherein the stall fraction for the next program execution phase is predicted according to a moving average based on the measured stall fraction and the predicted stall fraction for the current program execution phase.

34. The non-transitory computer-readable medium recited in claim 33, wherein the moving average is an exponential moving average calculated according to the formula:

PredStall_n+1=α

*Stall_n+(1−

α

)*PredStall_n,

where α

is a constant value, Stall_n is the measured stall fraction for the current program execution phase, and PredStall_n is the predicted stall fraction for the current program execution phase.

35. The non-transitory computer-readable medium recited in claim 31, wherein the predicted stall fraction for the current program execution phase is calculated in a preceding program execution phase.

36. The non-transitory computer-readable medium recited in claim 31, wherein the frequency setting and the voltage setting to be applied during the next program execution phase is mapped to the predicted stall fraction for the next program execution phase.

37. The non-transitory computer-readable medium recited in claim 31, further comprising code for causing the processor to:

compare the predicted stall fraction for the next program execution phase to multiple different thresholds that correspond to different frequency and voltage setting combinations; and

map the predicted stall fraction for the next program execution phase to one of the multiple different frequency and voltage setting combinations that has a maximum power savings, a minimum performance loss, or a combination thereof at the predicted stall fraction.

38. The non-transitory computer-readable medium recited in claim 31, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which a dispatch stall occurred.

39. The non-transitory computer-readable medium recited in claim 31, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based at least in part on a number of cycles during the current program execution phase in which an oldest instruction in a load queue was a last-level cache miss.

40. The non-transitory computer-readable medium recited in claim 31, wherein the measured stall fraction indicates the degree to which the current program execution phase was memory-bound based on a number of cycles during the current program execution phase in which a dispatch stall occurred while an oldest instruction in a load queue was a last-level cache miss.