EFFECTIVENESS AND PRIORITIZATION OF PREFETCHES

• US 20180074826A1
• Filed: 11/03/2017
• Published: 03/15/2018
• Est. Priority Date: 06/28/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: GSCHWIND, Michael K., JACOBI, Christian, SAPORITO, Anthony, SHUM, Chung-Lung K.
• Granted Patent: US 10,372,457 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

Claims

1. A computer-implemented method comprising:

issuing, by a processor, a prefetch instruction;

fetching, by the processor, based on the prefetch instruction, elements from a cache, wherein the cache comprises a memory or a higher level cache;

storing, by the processor, the elements in a temporary storage and monitoring the elements for accesses by an instruction issued by the processor;

storing, by the processor, a record representing the prefetch instruction;

updating, by the processor, the record with an indicator; and

issuing, by the processor, a new prefetch instruction, wherein the issuing comprises;

comparing, by the processor, the new prefetch instruction to the record;

based on the new prefetch instruction matching the prefetch instruction, assigning, by the processor, the indicator to the new prefetch instruction as a priority value of the new prefetch instruction;

based on the new prefetch instruction not matching the prefetch instruction, assigning, by the processor, a default value to the new prefetch instruction as the priority value of the new prefetch instruction; and

determining, by the processor, whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

2. The computer-implemented method of claim 1, wherein the updating the record with the indicator is based on one of:

the temporary storage losing the elements before the elements are accessed by the instruction, or an address of the instruction matching an address of the prefetch instruction.

3. The computer-implemented method of claim 1, further comprising:

executing, by the processor, the new prefetch instruction, based on the determining indicating that the priority value is above a predefined threshold.

4. The computer-implemented method of claim 1, the storing the record representing the prefetch instruction further comprising:

indexing, by the processor, the record by an address of the prefetch instruction.

5. The computer-implemented method of claim 1, wherein the storing the record representing the prefetch instruction comprises:

storing, by the processor, the record in a data structure wherein the data structure is one of;

a dedicated data structure or a shared data structure.

6. The computer-implemented method of claim 2, wherein the updating the record with the indicator is based on the address of the instruction matching the address of the prefetch instruction, and wherein the indicator comprises a number of cycles from the issuing the prefetch instruction to issuing the instruction.

7. The computer-implemented method of claim 1, the determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction, further comprises:

checking, by the processor, fetch control resources to determine if a fetch control resource is available to execute the new prefetch instruction;

based on determining that the fetch control resources are not available, obtaining priority values of prefetch instructions in progress with the fetch control resources;

identifying, by the processor, a prefetch instruction in progress of the prefetch instructions in progress with a lowest priority value and comparing the lowest priority value with the priority value of the new prefetch instruction;

based on determining, by the processor, that the priority value of the new prefetch instruction is higher than the priority value of the identified prefetch instruction in progress, cancelling, by the processor, execution of the identified prefetch instruction; and

determining, by the processor, whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

8. The computer-implemented method of claim 1, further comprising:

fetching, by the processor, based on the new prefetch instruction, new elements from the cache;

storing, by the processor, the new elements in the temporary storage and monitoring the new elements for accesses by instructions issued by the processor;

storing, by the processor, a new record representing the new prefetch instruction; and

updating, by the processor, the new record with a new indicator.

9. The computer-implemented method of claim 8, wherein the new indicator is based on one of:

the temporary storage losing the new elements before the elements are accessed by at least one instruction, or an address of at least one instruction matching an address of the prefetch instruction.

10. The computer-implemented method of claim 9, further comprising:

issuing, by the processor, another prefetch instruction, wherein the issuing comprises;

comparing, by the processor, the other prefetch instruction to the record and to the new record;

based on the other prefetch instruction matching one of the prefetch instruction or the new prefetch instruction, assigning, by the processor, one of the indicator or the new indicator to the other prefetch instruction as a priority value of the other prefetch instruction;

based on the other prefetch instruction not matching one of the prefetch instruction or the new prefetch instruction, assigning, by the processor, the default value to the other prefetch instruction as the priority value of the other prefetch instruction; and

determining, by the processor, whether to execute the other prefetch instruction, based on the priority value of the other prefetch instruction.