NEURAL NETWORK HARDWARE ACCELERATOR ARCHITECTURES AND OPERATING METHOD THEREOF

• US 20180075339A1
• Filed: 08/11/2017
• Published: 03/15/2018
• Est. Priority Date: 09/09/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: MA, Kenneth C., SUH, Dongwook
• Granted Patent: US 11,501,130 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2207/4824 Neural networks
• CPC Class Codes: G06F 7/026 Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/048 Activation functions
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/06 Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G06N 5/04 Inference or reasoning models
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements

Abstract

A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values.

Claims

1. An operating method of a memory-centric neural network system comprising:

providing a processing unit;

providing semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit;

connecting weight matrixes including a positive weight matrix and a negative weight matrix to Axons and Neurons, the weight matrixes are constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of the Axons, outputs of the memory cells of a same column are connected to one of the Neurons;

registering timestamps of the Axons and the Neurons into timestamp registers;

looking up adjusting values from a lookup table, the adjusting values of the lookup table are indexed in accordance with the timestamps; and

updating the weight matrixes in accordance with the adjusting values by the processing unit.

2. The method of claim 1, wherein the registering the timestamps includes

generating a selected axon timestamp from axon timestamps, each of the axon timestamps is corresponding to one of the Axons,

generating neuron timestamps for the Neurons, each of the neuron timestamps is corresponding to one of the Neurons, and

comparing the selected axon timestamp with each of the neuron timestamps by a comparison circuit, when one of the Axons fires, or one of the Neurons fires, or the combination thereof fire, and the selected axon timestamp and at least one of the neuron timestamps are non-zero.

3. The method of claim 1, wherein the registering the timestamps includes registering a predetermined value when a corresponding Axon or a corresponding Neuron fires, and generating the timestamp for each of the Axons or the Neurons by decreasing the predetermined value at each of subsequent timesteps by a time stamping circuit.

4. The method of claim 1, wherein the connecting the weight matrixes includes connecting a Resistive random-access memory (ReRAM), and the memory cells are memristors.

5. The method of claim 1, wherein the looking up the adjusting values from the lookup table includes generating comparing results of a selected axon timestamp and each of neurons timestamps, and determining the adjusting values in accordance with the comparing results.

6. The method of claim 5, wherein the updating the rows of the weight matrixes includes

increasing weights of the row of the weight matrixes of the selected axon for a next step by the adjusting values, when the comparing results is positive, and

decreasing the weights of the rows of the weight matrixes of the selected axon for the next step by the adjusting values, when the comparing results is negative.

7. The method of claim 1, wherein the registering the timestamps include selecting one of the Axons for updating a corresponding row of the weight matrixes by a selective circuit, and repeatedly selecting another one of the Axons until all of the Axons are selected.

8. The method of claim 1, wherein the connecting the weight matrixes includes

connecting the inputs of the memory cells at the same row of the positive weight matrix and the negative weight matrix to one of the corresponding Axons, and

connecting the outputs of the memory cells at the same column of the positive weight matrix to one of the corresponding Neurons as a positive neuron value, and connecting the outputs of the memory cells at the same column of the negative weight matrix to the same corresponding Neuron as a negative neuron value.

9. The method of claim 8, further comprising:

subtracting the negative neuron value from the positive neuron value of the same corresponding Neuron by a subtractor, and generating a subtraction result,

compensating the subtraction result with a leak value by an adder, and generating a Vmem for each of the Neurons, and

comparing the Vmem with a threshold value Vth by a comparison circuit, the corresponding Neurons fire when the Vmem thereof is greater than the threshold value Vth.

10. The method of claim 1, wherein the updating the weight matrixes includes updating the row of the weight matrixes of a selected Axon with the adjusting values when at least one of the adjusting values is non-zero, and skipping to another row of the weight matrixes of another selected Axon when none of the adjusting values is non-zero.

15. The system of claim 1, wherein the adjusting values of the lookup table is determined by generating comparing results of a selected axon timestamp and each of neurons timestamps, and determining the adjusting values in accordance with the comparing results.

16. The system of claim 15, wherein the rows of the weight matrixes are updated with the adjusting values includes

increasing weights of the row of the weight matrixes of the selected axon for a next step by the adjusting values, when the comparing results is positive, and

decreasing the weights of the rows of the weight matrixes of the selected axon for the next step by the adjusting values, when the comparing results is negative.

11. A memory-centric neural network system comprising:

a processing unit;

semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit;

weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons;

timestamp registers registering timestamps of the Axons and the Neurons; and

a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values.

12. The system of claim 11, wherein the timestamp registers include

axon timestamp registers registering axon timestamps, each of the axon timestamps is corresponding to one of the Axons, a selected axon timestamp is selected from the axon timestamps,

neuron timestamp registers registering neuron timestamps, each of the neuron timestamps is corresponding to one of the Neurons, and

a comparison circuit comparing the selected axon timestamp with each of the neuron timestamps, when one of the Axons fires, or one of the Neurons fires, or the combination thereof fire, and the selected axon timestamp and at least one of the neuron timestamps are non-zero.

13. The system of claim 11, wherein the timestamp registers register a predetermined value when a corresponding Axon or a corresponding Neuron fires, and a time stamping circuit generating the timestamp for each of the Axons or the Neurons by decreasing the predetermined value at each of subsequent timesteps.

14. The system of claim 11, wherein the weight matrixes include a Resistive random-access memory (ReRAM), and the memory cells are memristors.

17. The system of claim 11, wherein the timestamp registers include a selective circuit selecting one of the Axons for updating a corresponding row of the weight matrixes, and repeatedly selecting another one of the Axons until all of the Axons are selected.

18. The system of claim 11, wherein the weight matrixes

connecting the inputs of the memory cells at the same row of the positive weight matrix and the negative weight matrix to one of the corresponding Axons, and

connecting the outputs of the memory cells at the same column of the positive weight matrix to one of the corresponding Neurons as a positive neuron value, and connecting the outputs of the memory cells at the same column of the negative weight matrix to the same corresponding Neuron as a negative neuron value.

19. The system of claim 18, wherein each of the Neurons includes

a subtractor subtracting the negative neuron values from the positive neuron values of the same column, and generating a subtraction result,

an adder compensating the subtraction result with a leak value, and generating a Vmem for each of the Neurons, and

a comparison circuit comparing the Vmem with a threshold value Vth, the corresponding Neurons fire when the Vmem thereof is greater than the threshold value Vth.

20. The system of claim 11, wherein the weight matrixes are updated by updating the row of the weight matrixes of a selected Axon with the adjusting values when at least one of the adjusting values is non-zero, and skipping to another row of the weight matrixes of another selected Axon when none of the adjusting values is non-zero.