NEURAL NETWORK HARDWARE ACCELERATOR ARCHITECTURES AND OPERATING METHOD THEREOF
First Claim
1. An operating method of a memory-centric neural network system comprising:
- providing a processing unit;
providing semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit;
connecting weight matrixes including a positive weight matrix and a negative weight matrix to Axons and Neurons, the weight matrixes are constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of the Axons, outputs of the memory cells of a same column are connected to one of the Neurons;
registering timestamps of the Axons and the Neurons into timestamp registers;
looking up adjusting values from a lookup table, the adjusting values of the lookup table are indexed in accordance with the timestamps; and
updating the weight matrixes in accordance with the adjusting values by the processing unit.
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Accused Products
Abstract
A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values.
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Citations
20 Claims
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1. An operating method of a memory-centric neural network system comprising:
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providing a processing unit; providing semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; connecting weight matrixes including a positive weight matrix and a negative weight matrix to Axons and Neurons, the weight matrixes are constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of the Axons, outputs of the memory cells of a same column are connected to one of the Neurons; registering timestamps of the Axons and the Neurons into timestamp registers; looking up adjusting values from a lookup table, the adjusting values of the lookup table are indexed in accordance with the timestamps; and updating the weight matrixes in accordance with the adjusting values by the processing unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 16)
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11. A memory-centric neural network system comprising:
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a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values. - View Dependent Claims (12, 13, 14, 17, 18, 19, 20)
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Specification