SEMICONDUCTOR DEVICE

• US 20180076201A1
• Filed: 09/06/2017
• Published: 03/15/2018
• Est. Priority Date: 09/14/2016
• Status: Active Application

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: TOYODA, Yoshiaki, KATAKURA, Hideaki
• Application Number:
  US15/696,534
• Publication Number:
  US 20180076201A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series

Abstract

A semiconductor device includes a lateral MOSFET and a vertical semiconductor device that are formed on the same semiconductor substrate. In the lateral MOSFET, the voltage of a back-gate electrode is set to be higher than the voltage of a source electrode and a gate electrode by greater than or equal to a prescribed value (greater than or equal to 40V). A drain-side diffusion region, a drain diffusion region, a drain electrode, a gate insulating film, a gate electrode, and a LOCOS film are formed in annular shapes centered on a source diffusion region. As a result, an active channel region between the drain diffusion region and the source diffusion region as well as peripheral portions of the LOCOS film are also annular-shaped.

Claims

1. A semiconductor device having a lateral semiconductor device and a vertical semiconductor device formed on a semiconductor substrate of a first conductivity type,

wherein the lateral semiconductor device comprises:

a first diffusion region of a second conductivity type selectively formed in a surface layer of one principal surface of the semiconductor substrate;

a second diffusion region of the second conductivity type selectively formed separated from the first diffusion region in the surface layer of the one principal surface of the semiconductor substrate;

a third diffusion region of the second conductivity type selectively formed within the first diffusion region and at a higher impurity concentration than the first diffusion region;

a fourth diffusion region of the second conductivity type selectively formed within the second diffusion region and at a higher impurity concentration than the second diffusion region;

a local insulating film selectively formed around a periphery of the lateral semiconductor device on the one principal surface of the semiconductor substrate, and also selectively formed on a portion of the one principal surface of the semiconductor substrate positioned between the third diffusion region and the fourth diffusion region; and

a gate electrode formed on at least a portion of the one principal surface of the semiconductor substrate positioned between the first diffusion region and the second diffusion region, with a gate insulating film interposed therebetween, the gate electrode also being formed on a portion of a surface of the local insulating film with the gate insulating film interposed therebetween,

wherein the semiconductor device is configured to receive a voltage on another principal surface of the semiconductor substrate that is set to be higher than voltages of the gate electrode, the third diffusion region, and the fourth diffusion region by greater than or equal to a prescribed value, and

wherein the first diffusion region, the third diffusion region, the gate electrode, and the local insulating film are formed in annular shapes surrounding the fourth diffusion region in a planar pattern.

2. The semiconductor device according to claim 1,

wherein the third diffusion region is a drain diffusion region,

wherein the fourth diffusion region is a source diffusion region, and

wherein, on the portion of the one principal surface of the semiconductor substrate positioned between the third diffusion region and the fourth diffusion region, the local insulating film is selectively formed on a portion of the first diffusion region other than where the third diffusion region is formed.

3. The semiconductor device according to claim 1,

wherein the third diffusion region is a source diffusion region,

wherein the fourth diffusion region is a drain diffusion region, and

wherein, on the portion of the one principal surface of the semiconductor substrate positioned between the third diffusion region and the fourth diffusion region, the local insulating film is selectively formed on a portion of the second diffusion region other than where the fourth diffusion region is formed.

4. The semiconductor device according to claim 1,

wherein, on the portion of the one principal surface of the semiconductor substrate positioned between the third diffusion region and the fourth diffusion region, the local insulating film is selectively formed on a portion of the first diffusion region other than where the third diffusion region is formed, and is also selectively formed on a portion of the second diffusion region other than where the fourth diffusion region is formed,

wherein the gate electrode is formed to cover at least a portion of a surface of the local insulating film that is selectively formed on the portion of the first diffusion region and a portion of a surface of the local insulating film that is selectively formed on the portion of the second diffusion region, and

wherein the third diffusion region, the gate electrode, and the local insulating film are formed symmetrically about the fourth diffusion region in a planar pattern.

5. The semiconductor device according to claim 2,

wherein the lateral semiconductor device further includes:

a fifth diffusion region of the first conductivity type selectively formed in the surface layer of the one principal surface of the semiconductor substrate, the fifth diffusion region being separated from the first diffusion region and the second diffusion region; and

a back-gate electrode contacting the fifth diffusion region, and

wherein the second diffusion region and the fourth diffusion region are formed in annular shapes surrounding the fifth diffusion region in a planar pattern.

6. The semiconductor device according to claim 1,

wherein the first conductivity type is n-type, and

wherein the second conductivity type is p-type.

7. The semiconductor device according to claim 1, wherein the prescribed value is greater than or equal to 40V.

9. The semiconductor device according to claim 4,

wherein the third diffusion region is a drain diffusion region, and

wherein the fourth diffusion region is a source diffusion region.

8. An operation amplifier, comprising

an input differential stage;

a p-channel MOSFET connected to the input differential stage; and

an n-channel MOSFET connected to the input differential stage, wherein the input differential stage includes a lateral p-type MOSFET device that comprises;

a first diffusion region of p-type selectively formed in a surface layer of one principal surface of a semiconductor substrate of n-type;

a second diffusion region of p-type selectively formed separated from the first diffusion region in the surface layer of the one principal surface of the semiconductor substrate;

a third diffusion region of p-type selectively formed within the first diffusion region and at a higher impurity concentration than the first diffusion region;

a fourth diffusion region of p-type selectively formed within the second diffusion region and at a higher impurity concentration than the second diffusion region;

a local insulating film selectively formed around a periphery of the lateral semiconductor device on the one principal surface of the semiconductor substrate, and also selectively formed on a portion of the one principal surface of the semiconductor substrate positioned between the third diffusion region and the fourth diffusion region; and

a gate electrode formed on at least a portion of the one principal surface of the semiconductor substrate positioned between the first diffusion region and the second diffusion region, with a gate insulating film interposed therebetween, the gate electrode also being formed on a portion of a surface of the local insulating film with the gate insulating film interposed therebetween,

wherein the operational amplifier is configured such that another principal surface of the semiconductor substrate of the lateral p-type MOSFET device receives a voltage that is set to be higher than voltages of the gate electrode, the third diffusion region, and the fourth diffusion region by greater than or equal to a prescribed value, and

wherein the first diffusion region, the third diffusion region, the gate electrode, and the local insulating film are formed in annular shapes surrounding the fourth diffusion region in a planar pattern.