PIXEL STRUCTURE AND RELATED FABRICATION METHOD

• US 20180076224A1
• Filed: 06/19/2017
• Published: 03/15/2018
• Est. Priority Date: 09/09/2016
• Status: Active Application

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: I, Chu-Hsuan, CHEN, Yi-Wei
• Granted Patent: US 10,276,600 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A pixel structure includes a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The second metal layer is disposed on the first insulating layer, and the second metal layer includes at least one first data line, at least one source, and at least one first drain, wherein the first data line is electrically connected to the source. The second insulating layer is disposed on the second metal layer, the second insulating layer includes at least one opening that is disposed corresponding to the first drain, and the area of the opening is greater than the area of the first drain. The third metal layer includes at least one second drain that is electrically connected to the first drain, the second drain is disposed corresponding to the opening and disposed on the first drain.

Claims

1. A pixel structure, disposed on a substrate, comprising:

a patterned semiconductor layer disposed on the substrate;

a gate insulating layer disposed on the patterned semiconductor layer;

a first metal layer disposed on the gate insulating layer, wherein the first metal layer has at least one gate line and at least one gate, and the gate is electrically connected to the gate line;

a first insulating layer disposed on the first metal layer;

a second metal layer disposed on the first insulating layer, wherein the second metal layer has at least one first data line, at least one source, and at least one first drain, wherein the first data line is electrically connected to the source, and the first drain and the first data line are distanced away from each other for a first distance D1 in a first direction;

a second insulating layer disposed on the second metal layer, wherein the second insulating layer has at least one patterned opening disposed corresponding to the first drain, and the patterned opening is larger than the first drain;

a third metal layer, having at least one second drain electrically connected to the first drain, wherein the second drain is disposed corresponding to the patterned opening and on the first drain, the second drain and the first data line are distanced away from each other for a second distance D2 in the first direction, and the second distance D2 is less than the first distance D1;

a third insulating layer disposed on the third metal layer; and

a pixel electrode disposed on the third insulating layer, wherein the pixel electrode is electrically connected with the second drain.

2. The pixel structure according to claim 1, wherein the first distance D1 is subtracted from the second distance D2 to obtain a distance difference P, and the distance difference P is greater than or equal to 2 microns.

3. The pixel structure according to claim 1, wherein the second insulating layer covers the source and the first data line.

4. The pixel structure according to claim 1, wherein the first drain has a first line width W1, the second drain has a second line width W2, and the second line width W2 is greater than the first line width W1.

5. The pixel structure according to claim 4, wherein the second line width W2 and the first line width W1 have a ratio R, and the ratio R satisfies 3≧

R≧

1.5.

6. The pixel structure according to claim 1, wherein the first data line extends along a second direction, the gate line along the first direction, and the first data line intersects with the gate line.

7. A pixel structure, disposed on a substrate, comprising:

a patterned semiconductor layer disposed on the substrate;

a gate insulating layer disposed on the patterned semiconductor layer;

a first metal layer disposed on the gate insulating layer, wherein the first metal layer has at least one gate line and at least one gate, and the gate is electrically connected to the gate line;

a first insulating layer disposed on the first metal layer;

a second metal layer disposed on the first insulating layer, having at least one drain, a first source, and a second source, wherein the first source and the second source are arranged side by side in a first direction and distanced away from each other for a first distance D1;

a second insulating layer disposed on the second metal layer and the first insulating layer, wherein the second insulating layer has multiple patterned openings, and the patterned openings are disposed corresponding to the first source and the second source respectively;

a third metal layer disposed on the second metal layer, the first insulating layer, and the second insulating layer, wherein the third metal layer is disposed corresponding to the patterned openings, and the third metal layer has a first data line, a second data line, a third source, and a fourth source;

a third insulating layer disposed on the third metal layer; and

a pixel electrode disposed on the third insulating layer, wherein the pixel electrode is electrically connected with the drain;

wherein the first data line and the second data line are disposed on the first insulating layer and arranged in parallel corresponding to the patterned openings respectively in the first direction;

wherein the third source and the fourth source are disposed on the first source and the second source respectively, corresponding to the patterned openings, and distanced away from each other for a second distance D2; and

wherein the first distance D1 is greater than the second distance D2.

8. The pixel structure according to claim 7, wherein D1≦

(Q*D2), and Q≧

2.

9. The pixel structure according to claim 7, wherein the first data line is electrically connected to the first source and the third source, and the second data line is electrically connected to the second source and the fourth source.

10. The pixel structure according to claim 7, wherein the drain is disposed between the first data line and the second data line in the first direction.

11. The pixel structure according to claim 7, wherein the second insulating layer covers the drain.

12. The pixel structure according to claim 7, wherein the first source and the second source have a first line width W1, the third source and the fourth source have a second line width W2, and the second line width W2 is greater than the first line width W1.

13. The pixel structure according to claim 12, wherein the second line width W2 and the first line width W1 have a ratio R, and the ratio R satisfies 3≧

R≧

1.5.

14. The pixel structure according to claim 7, wherein the first data line and the second data line extend along a second direction, the gate line extends along the first direction, and the first data line and the second data line intersect with the gate line.